SUNNYVALE, Calif. The next big fight in the programmable-logic world will involve on-chip intellectual property cores for an FPGA and the interconnect needed to make them work, according to Tom Hart, president and chief executive officer of QuickLogic Corp. To that end, QuickLogic today (Oct. 28) disclosed an FPGA that combines 200,000 gates of programmable logic and a hard-wired 32-bit PCI controller in a 280-pin package.
QuickLogic has been down this integration path before. It has fielded FPGAs that include a pre-verified MIPS processor core and two Ethernet MACs on one chip. Assuming that few engineering teams can afford to design cores that have been standardized and are widely available, the company has placed them on-chip.
"If you were an engineering manager, why would you want to design and verify a 10/100 MAC?," Hart asked in a recent presentation at the company's headquarters here.
Melding an FPGA and hard ASIC gates can reduce power consumption and raise performance, QuickLogic said. A standalone 32-bit MIPS processor running full speed has a throughput of 16-Mbits/second; putting the same processor on an FPGA die yields 300 Mbits/s of throughput while using only 10 percent of the CPU's horsepower, Hart said.
"This is how you get to higher performance without jacking up the power," he said.
QuickLogic said better performance is a key attribute of its new QL5632 device, which is available now in a PBGA or PQTP package for $21 each in 25,000-unit quantities.
The addition of a PCI core to an FPGA is not in itself groundbreaking. FPGA makers Altera Corp. and Xilinx Inc. have been porting soft PCI controllers into their devices for years. But programming soft intellectual property cores into SRAM-based FPGAs can take months of design and debug work, QuickLogic said. Worst, this approach poses "a very serious risk" that standard PCI plug-in cards will be rendered inoperable because of the delay imposed while an SRAM-based FPGA is being loaded by an external PROM device. In contrast, QuickLogic said its FPGAs are programmed through a layer of amorphous silicon, so the configuration data is etched permanently into the FPGA whether the power is on or off.
The downside to this approach is that QuickLogic's FPGAs can only be programmed once, whereas SRAM-based FPGAs can be reconfigured in the field or in the lab, over and over again.
Hart said reprogrammability is a marketing "red herring" and that most customers don't need it. With customers such as Emulex, Nortel and Teradyne, Hart said QuickLogic has proven as much.
"Xilinx has convinced the world that a lemon called volatility is lemonade called reprogrammability," Hart said.
Routing is another area where QuickLogic's architecture shines, Hart said. An amorphous silicon layer is built up vertically between metals and acts as a transistor-less switch, so there are fewer limits to the amount of routing that can be done compared to mainstream FPGAs, which need a six-transistor SRAM cell for every switch. That's why QuickLogic can bolt a MIPS processor and two 10/100 Ethernet controller MACs to its FPGA, while Altera has only been able to integrate an ARM processor, Hart said.
QuickLogic's approach also confers four times more density than SRAM-based FPGAs, making it more silicon efficient. "They're building a strip mall and we're building a high-rise," Hart said at a recent investors conference. On paper this gives QuickLogic a big cost advantage over its larger rivals, but Hart said he's not willing to engage in a price war with Altera and Xilinx, which got an earlier start in the market.
This partly explains QuickLogic's dogged pursuit of on-chip embedded cores over conventional blank-slate FPGAs. Pushing aside his plate of meatloaf and mashed potatoes, Hart unfolded a napkin and scribbled two balance sheets showing the rough cost of revenue incurred by his company against one of his big rivals. His conclusion: his competitor could handily match his price cuts with minimal pain. "We'd be dead," he said.