SAN MATEO, Calif. - As operating frequencies on deep-submicron chips continue to rise and-more important-as edge rates spiral almost unnoticed, design teams and vendors alike are getting an uncomfortable feeling about parasitic extraction, signal integrity and even basic timing analysis, according to many industry leaders.
The problem has at least two facets, some say. First, and by far the best publicized, the increasingly dense three-dimensional structures that make up the metal stack in a 130-nanometer design have all sorts of parasitic impedances: resistance within the copper itself, capacitance between a metal segment and substrate, capacitance between nearby metal segments, self-inductance and, many fear, significant mutual inductance to other, not necessarily nearby metal structures.
This by itself is creating a problem, not so much of physics but of scale. Tool developers are reporting huge growth in the size of the files used and produced during the extraction process even when very aggressive approximations are employed. This affects the amount of resources needed to achieve signal integrity and timing estimates, and raises questions about their reliability.
Into RF zones
But another factor has reared its head at recent conferences. Even with clock frequencies in the hundreds of megahertz, edge rates are getting so high on 130-nm processes that much of the energy of a pulse train occurs at frequencies where only RF design tools are appropriate. Thus transmission-line effects and, more recently, skin effect have become significant issues in interconnect modeling.
Nowhere is this more of an issue than in analog design. "We are seeing this even in the problem of circuit sizing for analog design,"said Aykut Dengi of Neolinear Inc. (Tempe, Ariz.) in a recent interview. "Passive components are interacting with each other and with the wires, and at today's frequencies, these interactions can have a first-order impact on sizing."
Dengi said the rather simplistic model extraction and sizing tools used in the past may still work for an initial pass, but were already failing in verification and might not converge into a correct result if used in an iterative, automated sizing algorithm. Field solvers, he said, gave much more reliable results in general, but were not intended for use in IC structures or optimized for that purpose. This mismatch could cause extended run-times, Denge claimed.
This point was corroborated by papers at the recent ICCAD conference in San Jose, Calif., where much work was shown on novel mathematical approaches to avoid the mechanical-CAD-like surface meshes created by many conventional algorithms. The result of exploring different kinds of discrete approximations to fields usually was a huge series of integral equations that in turn required their own digital solver algorithm.
If the bottom line is that there is not enough time for any field solver approach, Dengi suggested that it may be necessary to constrain designs to using only patterns that have been solved ahead of time and placed in a library. This approach is already being used in standard-cell development, but may also have to be extended to interconnect and to the design of passive components on the die.
Whether, in particular, routing tools can adapt to using a fixed collection of patterns instead of an optimization scheme based on paths between endpoints remains to be seen. The approach would appear to be at least similar to the routing algorithm used in the Plato router-but when it comes to the art of routing, "similar" and "compatible" are very different things.