SAN JOSE, Calif. As if substrate coupling, capacitive coupling and mutual inductance weren't problems enough, a speaker at the fetchingly-titled ''A to Z of SoCs'' session at ICCAD here on Wednesday (Nov.13) identified another signal integrity threat that he called the most worrisome yet. John Cohn, distinguished engineer at IBM Microelectronics, warned that noise coupling through supply lines was a growing issue in 130-nm designs, and was very hard to analyze or attack.
''Series-RL coupling through the power supply grid is a very troubling problem,'' Cohn said. ''It virtually never happened at 0.25-micron. Maybe we saw one or two instances at 0.18-micron. But now in 0.13-micron designs, it's not unusual to have tens or hundreds of nets impacted by this mechanism on a single design.''
Cohn described the mechanism as starting with the huge changes in supply current that can occur very quickly in operating SoC cores, often in response to a subtle change in state. This may be particularly true when the core contains a large amount of dynamic logic, but is a serious problem with seemingly stable conventional logic and even SRAM. If a change of state causes a large number of simultaneous transitions within the core, there will be a substantial spike in supply current.
Adding to the problem is the growing use of clock and power supply gating techniques as part of aggressive power management strategies. If a large block of logic or RAM is put to sleep by turning off the supply current with a gating transistor, and then is revived suddenly, there can be a powerful transient on the supply grid all the way back to the package pins.
These powerful transients make accurate RLC modeling of the supply grid, lead frame and even the environment on the circuit board absolutely essential, Cohn said. He warned that it might take considerable attention and real estate to provide enough bypass capacitance on supply lines to damp the transients before they can get into other cores and cause trouble. In some cases, major revisions to floorplans, or even radical steps such as staggering logic transitions may be necessary.
Cohn cited one case in which an IBM design included large blocks of on-chip SRAM, placed on the die near a bank of 3 GHz I/O transceivers. When the SRAM switched, the resulting supply transient appeared as a 130 mV supply drop at the I/O blocks, causing the phase-locked-loops to lose lock and begin searching. In that design it proved necessary to move the SRAM blocks away from that edge of the die and to provide substantial capacitance on the supply lines.