EDA vendors may not want you to know about a paper from the recent Design and Verification Conference & Exhibition (DVCon) and available at the author's Web site. In it, Cisco Systems Inc. hardware engineer Rajesh Bawankule shows you how to "speed up Verilog simulation by 10x to 100x without spending a penny."
The paper illustrates a number of ways you can speed up simulation, without buying a faster simulator, workstation or accelerator or emulator. The first suggestion is to use profiling to eliminate simulation bottlenecks. In one example presented by Bawankule, 60 percent of the time was spent dumping the VCD format file, and discovering and fixing that problem doubled simulation speed.
Optimized compilation can provide another performance boost. The "Radiant" technology in Synopsys Inc.'s VCS simulator can provide a four- to 10-fold performance gain through its compile-time optimizations, Bawankule said.
Two-state simulation also saves time, resulting in a 20 to 200 percent speedup. You can compile most of your design in two-state mode, using four-state mode only when needed. Initializing registers and memories "in bulk" can provide another speedup, the paper says.
Efficient modeling is another trick. Bawankule says that removing I/O cell wrappers in design, and bit splicers in simulation testbenches, can boost speed 25 to 40 percent. Using switches properly is important, too. The presentation that comes with Bawankule's paper lists a number of switches that hinder performance, along with a few that help.
Not all programming language interfaces are required for a typical test suite, according to Bawankule. There's a way to find out which are needed. The paper also has a suggestion for speeding up Vera testbenches.
There's an interesting discussion about Linux machines vs. Sun Microsystems Inc. workstations for simulation. Bawankule says that Linux provides a twofold to fourfold speedup over Sun machines. The Linux machines, however, are less reliable, and they show dramatic degradation when multiple simulation jobs are executed. Firing up multiple simulations on a Linux box is not a good idea.
Presentations like this, where engineers provide practical tips from their own experience, can save a lot of time and money for EDA users. Before spending more money on tools, why not invest some time to make sure you're making the best use of what you've got?
You will find Bawankule's DVCon paper, along with a treasure trove of other practical information, at www.parmita.com/verilogcenter/papers.html.