ANAHEIM, Calif. The IEEE is pushing ahead to make Verisity Ltd.'s proprietary "e" an industry-standard verification language and to define the next revision of Verilog. But an apparent rift with the Accellera standards organization has raised the risk that Accellera's SystemVerilog 3.1 may diverge from the standard eventually approved by IEEE.
The standards jockeying will serve as a dramatic backdrop here next week as the 40th Design Automation Conference convenes.
Verisity will announce here that the IEEE Design Automation Standards Committee (DASC) has approved a project authorization request (PAR), named IEEE 1647, to develop a standard verification language based on "e." That's good news for the thousands of customers who have legacy "e" code. But some engineers question whether there will be a future need for "e," given that SystemVerilog 3.1 adds assertions and testbench constructs.
Meanwhile, the Verilog Standards Group (VSG)known also as IEEE 1364has announced a PAR to begin the next version of Verilog, to be called 1364-2005. In an announcement with no apparent input from Accellera, the VSG has called its own users' forum for Tuesday (June 3) at DAC and has put out a call for technology donations by August.
The VSG's announcement prompted Accellera chairman Dennis Brophy to call the VSG a "rogue IEEE operation" that is not following IEEE rules, and to ask Design Automation Standards Committee chairman Paul Menchini to "reconstitute" the group and hold an election for a new chairman.
Michael McNamara, who chairs IEEE 1364, countered that the VSG is following IEEE rulesand that it's time for Accellera to "put up or shut up" and donate SystemVerilog technology to the standards activities of the Institute of Electrical and Electronics Engineers.
Accellera's Brophy also said the IEEE Verification Language Study Group (VLSG), which initiated the "e" language standardization, violated IEEE rules by placing usage restrictions on the availability of "e" to committee members. Brophy himself is a member of the VLSG as well as a DASC steering committee member.
The Accellera board voted this week to approve SystemVerilog 3.1, along with Property Specification Language (PSL) 1.01, Standard Co-Emulation API (SCEAPI) 1.0 and Verilog-AMS 2.1. The board added a statement that "Accellera's policy is to transfer standards to the IEEE."
The two largest EDA vendors have taken different positions on Verilog. Synopsys Inc. strongly backs Accellera and is already implementing support for SystemVerilog 3.1, while Cadence Design Systems Inc., which has expressed concern about incompatible standards, has endorsed the IEEE 1364-2005 effort. All parties agree that there should be one, IEEE-approved Verilog standard, but questions of what, how, and when remain.
"I think the world would be best served if there was one set of committees that owned this [Verilog] language and moved it forward," said McNamara, who is senior vice president of technology at Verisity.
Opening and standardizing the proprietary "e" language will preserve "e" customers' investments and make it easier for third-party tools to support the language. But is this move too little, too late?
In a Synopsys User's Group trip report compiled by John Cooley in May, many engineers wrote in praise of "e," but many also said verification languages like "e" and Synopsys' Vera are doomed. "As soon as SystemVerilog is in place, nobody will pay extra for features which are already in their primary design language," wrote one engineer.
"Obviously there will be a need for 'e,' " responded Fran-
cine Ferguson, Verisity's vice president of corporate strategic marketing. "Verisity has the most advanced technology, the most advanced methodology, the largest amount of verification intellectual property. And SystemVerilog is still a long way from being an interoperable standard."
Ferguson said Verisity decided to open "e" because of customer demand. Part of openness is revealing what is in the "e" language, and Verisity is starting that this week with an "e" language tutorial at www.EEdesign.com. A forthcoming book by HDL expert Samir Palnitkar, titled Design Verification with e, will be published in August.
Verisity will announce a Coverage and Assertion Interface (CAI) next week that lets users import external coverage metrics and assertions into Verisity's Specman testbench development environment. Verisity and 0-In Design Automation will reveal an agreement by which 0-In's assertions can be brought into Specman via the CAI.
Brophy calls VSG a 'rogue operation.'
Brophy's complaint about the VSG is that committee chairman McNamara is not a "recognized member" of the DASC, as required by that organization, and that no Design Automation Standards Committee member actually voted for the 1364-2005 PAR.
But McNamara said he is indeed a DASC member, explaining that "the people who maintain business records for the DASC are not very efficient."
DASC's Menchini neither dismissed nor supported Brophy's complaints about the VSG. "Basically people have expressed some concerns, and [those concerns] are not frivolous," Menchini said. "I am . . . attempting to resolve the issues."