SANTA CRUZ, Calif. The Accellera Board of Directors voted Thursday (May 29) to approve the proposed SystemVerilog 3.1 standard. In addition, the board voted to approve the Property Specification Language (PSL) 1.01, the Standard Co-Emulation Application Programming Interface (SCE-API) 1.0, and Verilog-AMS 2.1.
Accellera approval of SystemVerilog 3.1 is a crucial step in moving this language, viewed as the next generation of Verilog, forward in the standardization process. But it has yet to be donated to the IEEE, whose Verilog Standards Group has received a project authorization request for the next version of Verilog, called 1364-2005.
SystemVerilog 3.1 adds high-level synthesizable constructs, testbench generation features, assertions and a C language API. An overview of SystemVerilog 3.1 is available in a tutorial article at EEdesign.
PSL, derived from IBM's Sugar language, is a formal language that lets design architects specify properties about a design. It also allows RTL designers to capture design intent in a verifiable form.
SCE-API defines a high-speed, asynchronous, transaction-level interface between simulators or testbenches, and hardware-assisted solutions such as emulation or rapid prototyping. It facilitates better re-use of models among different design tools.
Verilog-AMS models mixed-signal behavior. The newly-approved 2.1 standard improves the syntax and semantics of mixed-signal extensions to Verilog-AMS.
Accellera will hold an open meeting at next week's Design Automation Conference Wednesday, June 4, at 10:00 am in the Anaheim Convention Center. The IEEE VSG is holding a separate meeting Tuesday, June 3, at 1 pm at the Anaheim Hilton.