EDA vendors take notice: Ignoring FPGAs is risky business!
In 2002, there were 90,000 FPGA design starts, which represents a more than 10 to one ratio over ASIC design starts. New products from networking, wireless base-stations to mass storage, data communications and video servers are taking less time to get into production because the industry dynamics has changed, favoring an FPGA over an ASIC implementation.
What's changed? Electronics design engineers today face significant barriers when getting a product to market using ASICs. For example, ASIC designs suffer from insidious deep submicron effects that range from crosstalk and inductance to wire self heat and hot electrons.
Do you see a trend? I do, and believe electronic design automation (EDA) software and hardware vendors should quickly heed notice. EDA solutions developed specifically for FPGA design could obsolete ASIC technology for most standard products. A bold claim? Perhaps. Yet, current market statistics are decidedly moving in that direction.
Of course, EDA software and hardware is available now to support FPGA design, but ongoing investment isn't keeping pace with FPGA complexity. As market forecasts for FPGAs continue to climb, the discrepancy grows between hardware revenue and software revenue. In the ASIC realm, it's a 4X differential, while in FPGA, the differential is a shocking 65X. Consequently, today's EDA solutions don't properly support advanced high-speed, high-performance FPGA design.
FPGAs have long had an advantage over ASICs for both turnaround time and implementation. Technology breakthroughs from 10-million gate density to 400 MHz clock speeds enable FPGAs to handle many applications currently served by ASICs, while 300mm wafer sizes have made them readily affordable for volume production. It is becoming increasingly harder for design houses to justify an ASIC over an FPGA implementation.
The EDA industry's disregard for the FPGA market has produced a growing gap in the number of programmable transistors available to designers and the average number of transistors used by them. The increasing number of design iterations, sometimes as many as 50 per design, and the time for each iteration is undermining the fundamental FPGA advantage time to market.
Finally, ASIC production volumes and the price per part, which had previously been more cost effective than FPGA implementations, have risen consistently over the past few years with each technology shrink. In 1997, mask costs were pegged at $100,000 for 0.5-micron fabs. Today, it's closer to $1 million in 0.13-micron fabs, while FPGA pricing has been reduced with each new technology.
High-speed, high-performance FPGAs require ASIC-style solutions and methodologies. Just as ASIC design has fostered a team-based approach, multi-million gate FPGA designs require EDA software and hardware that can support a block-based, team approach. Solutions also need to be scalable and support both hierarchical design and block-based physical synthesis.
The new FPGA design paradigm will closely mirror that of the evolving ASIC design paradigm. Design planning will be used to bridge the gap between logic and physical design. A block-based methodology will be required to manage the complexity of multi-million gate designs.
Armed with this information, the EDA industry needs to respond by supporting and enabling its customer, the electronics design engineer, who is swiftly moving to FPGAs. This market is about to take off and the EDA industry should be there to help enable the FPGA momentum. Otherwise, ignoring FPGAs is risky business!
Jackson Kreiter is chairman and CEO of FPGA tools startup Hier Design.