SANTA CRUZ, Calif. FPGA tool startup Hier Design Inc. has announced enhancements to its PlanAhead software that help make it more appropriate for ASIC prototyping. PlanAhead is a hierarchical floorplanning and analysis tool aimed at complex FPGAs.
PlanAhead was initially introduced in July 2003. It takes EDIF netlists generated with FPGA synthesis tools, and automatically or manually partitions designs into hierarchical blocks to find the optimal floorplan for an FPGA design. It outputs an EDIF netlist optimized for an FPGA vendor's placement and routing tools.
Many FPGAs are used for ASIC prototyping, and Hier Design is now rolling out several enhancements aimed at supporting that function. One is a new schematic viewer. Another is a new feature that lets designers export intellectual property (IP) blocks as hard macros.
According to Salil Raje, Hier Design CTO, the company is also working on a feature that will allow designers to create Relatively Placed Macros (RPMs) for Xilinx FPGAs. It's expected to be available in early 2004, he said.
Raje said that PlanAhead is built for hierarchical place and route, and that it allows easy import and export of IP blocks. "Because PlanAhead makes no assumptions as to the completeness of the design, partial designs can go through the entire flow just as easily as complete designs," he noted.
With the new functionality, the floorplan and placement of an IP block can be preserved and retrieved into a new design, Raje said. The IP block can be moved within the FPGA with immediate guidance as to the optimal location of the block. "This functionality, a common task in the ASIC domain, had been nightmarishly difficult in the FPGA space," he said.