SAN JOSE, Calif. For the foreseeable future, there are no real "show stoppers" that will prevent the semiconductor industry from keeping pace with Moore's law, according to participants in a Monday night (Nov. 10) panel at the International Conference on Computer-Aided Design (ICCAD) here. The panel brought together semiconductor and EDA executives and academics.
Panel moderator John Darringer, an IBM research executive at the T.J. Watson Research Center, displayed a list of sticky issues manufacturability, variability, cost, power, productivity, analog design, and embedded software. He asked if panelists thought they were "show stoppers," causing the semiconductor industry to come screeching to a halt.
Panelists were quick to note that at every new technology node, someone inevitably points out some problem and calls it a potential "show stopper." But in every case the semiconductor industry, arguably with help from EDA vendors, overcomes the issue of the day and keeps pace with Moore's law.
While panelists didn't see any show stoppers, they did agree that manufacturability and variability in manufacturing processes will become increasingly worse as process geometries shrink from 90nm to 65nm and 45nm. Panelists said that even at 90nm, optical proximity correction (OPC) and phase shift mask are becoming a necessity, but the EDA industry has yet to really address the design for manufacturing issue sufficiently.
Indeed, semiconductor representatives on the panel criticized the EDA industry for a lack of tools addressing manufacturing variability, effective power analysis and leakage tools, and its inability to promptly produce a viable next generation design language above HDLs to better help designers produce huge SoCs.
"The EDA industry has a hard time understanding that as things get smaller they are harder to build," said panelist Kerry Bernstein, senior technology staff member at IBM's T.J. Watson research facility. "Thanks for that explanation," responded Cadence Design Systems co-CTO Aki Fujimura, to big laughs from the audience.
Fujimura and Joe Sawicki, vice president and general manager of Mentor's Design to Silicon group, defended the honor of the EDA industry by saying that the simiconductor industry is also to blame for delaying tool creation because semiconductor vendors have a hard time figuring out their own processes and exactly what problems tools need to address.
To further this point, Sawicki gave an example. He explained that leakage current was until recently considered a huge problem with new processes, and that semiconductor companies were screaming to the EDA industry to help create tools to properly account for leakage.
Sawicki said that his group, which creates the popular Calibre DRC/LVS tool, jumped headfirst at the problem and was getting Mentor tools ready to account for leakage. But, he said, last week Intel announced that they could nip the leakage problem in the bud by moving to high-k dielectric materials that don't leak.
Meanwhile, Sawicki and Fujimura said that the EDA industry continues to create tools to address new semiconductor problems as processes come online, but noted that the EDA industry certainly doesn't know the silicon problems before the silicon vendors do and that silicon vendors must better communicate with EDA vendors.
Fujimura added that Cadence is looking at power minimization technologies to help designers better deal with low power design as more functions make their way on chip.
Productivity was also a hot button with the panelists representing the semiconductor industry. Intel fellow and director of CAD research Bill Grundmann said that the EDA industry is sadly dragging its heels on creating a next generation design language above Verilog and VHDL.
"We are way overdue for the next level of abstraction," said Grundmann.
Meanwhile, ICCAD keynoter and Stanford professor Mark Horowitz argued that viable architecture tools, electronic system-level languages, and simply the creation of more intelligent chip architectures would help address many of the issues designers face further on in the design process.
Another notable banter began around the subject of mixed analog-digital design. One audience member said that it has become a common misconception that analog is reemerging as the dominant part of SoCs. He said that the most difficult analog functions are turned into digital and that analog still and "will always" remain 15 percent of a given SoC.
ICCAD is at the Doubletree Hotel in San Jose, Calif., through November 13.