High data-rate applications like Gigabit Ethernet, Infiniband, PCI Express, Fibre Channel and Serial ATA continue to drive system bandwidth to higher and higher levels, creating the need for high performance interconnect for line cards, chip-to-chip paths and switch fabrics. Taking parallel standards like ATA, PCI or GMII into the serial domain allows manufacturers to create systems with lower signal counts, simpler cabling and higher performance.
However, this higher speed performance comes at a price: signal integrity becomes a significant portion of the design effort and includes contributions from not only the ASIC, but the package and the printed circuit board (PCB) as well. Without careful design practices, program delays and rework will be inevitable. Time to market will also be impacted, which could lead to lost revenue.
High speed signaling has fast rise and fall times. This means that all loads must be treated as transmission lines rather than simple lumped models, which makes the analysis of the system more complex. PCB layout is more critical than ever, and ASIC tool flows have added signal integrity checking to their arsenals to help ensure a high quality product. But ensuring signal integrity on a few carefully placed high speed lines will pay dividends in a higher throughput, more compact system with state-of-the-art capability.
Signal integrity issues
Achieving high signal integrity requires careful tending to several parameters simultaneously. Neglecting any one of the key issues can result in unpredictable bit error rates or an unrealizable system. The key issues in a high-speed system are reflections and crosstalk. Each of these items can generate unwanted signals or noise.
Termination and reflections
Reflections are unwanted signals that are propagated on the signaling paths (or transmission lines) due to improper (unmatched) termination. At each point where there is an impedance mismatch, a reflection will be generated in the opposite direction of the transmitted signal. This signal will add to the main signal and can either reduce or increase its amplitude and can potentially cause problems at the receiver. This is commonly seen on an oscilloscope as "ringing" or overshoot on a signal.
Impedance mismatches can occur wherever there is a discontinuity in the circuit, such as at the wirebond to pad connection, wirebond to package lead frame, or anywhere on the ASIC or PCB where a component is added. On a PCB, this can include components like resistors or capacitors, vias between PCB layers, an unmatched trace, or a connector.
The signal path in most large networking switches consists of a line card (3" to 6" of PCB trace), a connector to the backplane, the backplane itself (20" to 30" of PCB trace), a connector to the switch fabric card, and the fabric card itself (3" to 6" of PCB trace). With up to 40 inches of PCB trace and two connectors, this signal path is difficult to drive and it requires close design attention to ensure the signal quality will be sufficient to create a system with a very low Bit Error Rate (BER). This is the number of errors per bit transmitted and it is less than one error in 1 x 10e12 bits in a Fibre Channel system.
Using internal termination is one way to help tame reflections. In the external termination diagram below, it can be seen that the driver output sees a load of the bond pad, bond wire and package characteristics before the line is terminated. Since the transmitting output drives a path of several components of various impedances and significant length (compared to the rise time of the signal), reflections will be set up on that line which will add disturbance to the original signal. Properly matched terminations will damp reflections so that the subsequent reflections will be insignificant.
Figure 1 -- Total driven load before the signal reaches an external termination resistor
By adding internal termination, the path before the termination is very short, so the disturbance to the driver is low and the signal will be less distorted than with external termination. Any reflections set up by the bond pad, bond wire, and package will be damped at the internal termination resistor and will not be sent out on the line again. Internal termination is one of the major reasons that IC manufacturers are able to drive high-speed signals from readily available wire bond packages.
To be most effective, high speed signaling buffers should have internal terminations whenever possible. Examples include the CML (Current Mode Logic) buffers of today's prevalent high-speed SerDes products; LVDS (Low Voltage Differential Signaling) buffers; new memory interface buffers for FCRAM (Fast Cycle Random Access Memory); and RLDRAM (Reduced Latency Dynamic RAM), which uses HSTL (High Speed Transceiver Logic) single ended signaling with on-die termination.
Figure 2 -- Short path from the driver output to the termination resistor
Crosstalk is an unwanted signal generated on a nearby (victim) line as a result of a transmitting line (aggressor). If the crosstalk is bad enough, false signaling can occur on the victim line. The potential for crosstalk is highest where a large amplitude signal line is near a high-impedance undriven line. The sharp rise time of the aggressor signal will couple into the victim trace through the parasitic capacitance or the mutual inductance, which are functions of the separation between traces and the dielectric constant of the separating material.
Figure 3 -- Effects that contribute to crosstalk
Crosstalk effects are functions of the rise and fall times of the aggressor, distance between the lines and the presence of signal reference planes. Careful control of these factors can maximize signal quality by minimizing the presence of unwanted crosstalk.
In today's high speed signaling environment, fast rise and fall times are a requirement. System clocks and system interconnect speeds continue to escalate. Even when the highest speeds are not required, the inherent high frequency capabilities of today's sub-micron processes exhibit rise and fall times that can impact signal integrity in many cases.
Limiting the rise times (slew rates) in some drivers is a requirement (as in PCI buffers), and in many cases this ability is desirable to minimize the EMI (Electro Magnetic Interference) effects. The lower the slew rates, the higher the effective impedance of the parasitic components, and the less signal that is transmitted through unwanted paths (including radiating off the PCB into the air).
Microstrip and stripline architectures are used on high-speed PC boards to reduce the crosstalk between traces. These techniques pair a signal trace with a solid reference plane above or below it. The reference plane can be any DC voltage since crosstalk is an AC effect, so usually the planes are ground or one of the power supplies.
The low impedance reference plane captures the return current of the signal trace. This current creates a magnetic field that opposes the field in the signal trace, and creates an overall field that is confined locally and falls off rapidly with distance. Microstrip architecture has one reference plane while stripline has two, one on each side of the signal trace (see figure below).
Figure 4 -- Cross-section view of PCB showing microstrip and stripline architectures
In these systems, the distance between two traces is a potent predictor of crosstalk between them. In a microstrip system, the crosstalk between two traces falls off approximately as the square of the distance and inversely as the distance to the reference plane (the closer the plane to the signal trace, the less the crosstalk).
A stripline system provides even better crosstalk protection since there is an extra reference plane to further confine the field generated by the signal trace. Obviously, stripline architecture, whether on a PCB or an IC package, provides the best crosstalk performance, but is more expensive than microstrip architecture. This tradeoff is typical in system design and in Integrated Circuit or ASIC designs it can be seen in the lower cost of a microstrip package versus a multi-layer, high performance stripline package.
Another technique for shielding victim lines from aggressor lines is to put low impedance traces between the interfering lines. Similar to the way a reference plane will contain the field generated by an active signal trace, the low impedance shield trace will also provide a path for return currents from the signal trace. This can help with crosstalk when microstrip, stripline, or enough distance cannot be used. Quantitatively, the other techniques will help the most, but where space is tight, it is a simple matter of running a power or ground trace between the affected traces (since they need to be present anyway).
For example, a high speed Serializer/Deserializer (SerDes) core might incorporate signal shielding between the sensitive receive inputs and the high speed, high-amplitude transmit pins. In the diagram below, note the fixed positions of the Tx and Rx lines and how the two low impedance supply pins separate them.
Figure 5 -- High-speed SerDes pinout showing isolating traces between the transmit pins and sensitive receive pins
Noise is any unwanted signal in a system, and it can be generated through many different avenues. Crosstalk is one way (as described above). Other sources of ASIC noise can transmit through the power supply lines (clock trees) and the ground planes (Simultaneously Switching Outputs, or SSO). When bit error rates rise in a system, it is usually due to some form of noise causing false switching. When the noise signal is large enough to cross a receiver threshold and mimic a purposely transmitted signal, errors will occur.
Power supply or digital core noise
As circuit geometries continue to shrink, metal thickness and pitch begin to limit the current carrying capabilities of the metal interconnect traces. This effect is somewhat mitigated by the decreasing power requirements of sub-micron circuits and the continual improvements in conductor materials, such as copper interconnect. However, as the geometries shrink, the ability to incorporate millions of additional circuit elements ensures that the power structures will still be stressed. Attention to the power delivery structure is more important than ever.
The biggest contributors to supply noise, or digital core noise, are clock trees in large digital designs, and large memory structures. Clock trees can generate large spikes of current when switching. Thousands of flops transitioning through the switching zone simultaneously can draw enough current to momentarily pull the core Vdd voltage down significantly. The scope photo below shows noise on the digital core supply caused by clock tree switching. The noise magnitude is about 110mV peak-to-peak on a 2.5V supply (4.4% of the supply).
Figure 6 -- Scope photo showing noise on the digital core voltage supply of an ASIC (110mV peak to peak)
Memories can also draw significant currents. For example, a 1 read, 1 write, high density SRAM might draw 20mAa average current when active, but can draw up to 343mAa of instantaneous current when being accessed. This supply "noise" can cause disruptions in sensitive analog circuits and can even adversely affect digital circuitry as well by altering thresholds or current drive ability. If the voltage drops too low, the circuitry will no longer be operating under the conditions for which it was designed resulting in poor performance or possibly non-performance.
Simultaneously switching outputs (SSO)
Simultaneously switching outputs, especially in large buses with high current drivers, can cause large perturbations of the ground potential on the chip. When the I/O buffers switch, they will all inject current into the package ground plane and chip substrate at the same time. Because of the inherent inductance and resistance in the package ground plane and the chip substrate, the ground potential can actually rise up.
The I/O power supply will also be pulled down as the buffers switch. This compression effect actually lowers the I/O supply voltage seen by the buffers. The reduced voltage on a buffer cell can cause a reduction in drive current, which increases propagation delay, increases rise and fall times, and creates an effect called "SSO pushout." This results in rising and falling signal edges that move out (or push out) in time, creating loss of timing margin by "closing" the "data eye" (clear area enclosed by the waveform).
This effect can look like jitter (seen as horizontal width of the waveform lines) in the eye diagram of the waveform shown below (an SSTL2 signal from an LSI Logic test chip). A perfect waveform would have lines that are very clean with very little width where the rising and falling lines cross. The cleaner the lines, the larger the eye and the easier it is to extract the correct data from the waveform.
The waveform below uses a signal:power:ground ratio of 1:1:1. In other words, for every signal pin (in this case for each SSTL2 buffer) there is one I/O power pin and one ground pin. This requirement obviously leads to a large power and ground overhead for the chip, but yields an extremely clean signal. The jitter in the waveform below is measured as the distance between the two vertical cursors, or 267ps.
Figure 7 -- Eye diagram captured from an SSTL2 buffer with a signal:power:ground ratio of 1:1:1
The next waveform is from a data bus that was constructed with an SSO ratio of 8:1:1, or one pair of I/O power and ground for every 8 signals. Here it can be seen that there is visibly more jitter in the waveform. This difference is due to SSO pushout. The jitter as measured by the two vertical cursors is 537ps. This is more than twice the jitter when using a 1:1:1 SSO ratio.
Figure 8 -- Eye diagram captured from an SSTL2 buffer with a signal:power:ground ratio of 8:1:1
The next waveform is captured from the bus using an SSO ratio of 4:1:1. This shows that the total jitter is 387ps, which places the value somewhere between the other two scenarios. When the entire timing budget is calculated, this SSO ratio may allow little enough jitter to make the parallel bus interface feasible without imposing impossible demands on the pin count of the device.
Figure 9 -- Eye diagram captured from an SSTL2 buffer with a signal:power:ground ratio of 4:1:1
Combating signal integrity issues in an ASIC
The primary way to minimize chip crosstalk effects is to avoid crosstalk through correct construction. Within the ASIC design flow, complex software tools are used to help reduce crosstalk by minimizing the driven net lengths based on drive strength, calculated delay times, and noise thresholds. One of the effects caused by crosstalk is incremental delay induced on a victim line. The delay due to crosstalk is calculated and the net length adjusted to make sure that the delay doesn't exceed a certain value (for example 100ps).
Crosstalk can also induce noise glitches in a victim line that exceed the switching threshold of the receiving logic element. This effect is checked based on aggressor/victim drive strength and relative position. The nets will be shortened and moved if required to reduce the crosstalk effects to acceptable levels.
Crosstalk avoidance is also done on a hierarchical level to create crosstalk immunity between upper level hard macros (a number of related circuit elements physically grouped together). This is done by analyzing the top level nets that travel between hard macros, and routing the signals to minimize critical net lengths and by ensuring that metal runs on adjacent layers are routed orthogonal (perpendicular) to minimize the parallel net length. At this top level, minimum block spacing is also confirmed to avoid block-to-block crosstalk.
The ASIC design tools will also minimize crosstalk generated on clock lines. Any noise on the clock lines will manifest itself as margin reducing jitter. Since clock lines are spread throughout the chip, they can be victim to many aggressor lines, so special care must be taken. Long clock nets should be identified and isolated with either with spacing or shielding.
As system-on-chip (SoC) devices increase in complexity, choosing the right semiconductor package becomes critical to ensure optimal system performance. With whole systems being integrated into single chip solutions, packaging technology needs to be considered up front. Delivering a complete SoC solution requires a co-design methodology between IP (Intellectual Property) developers and package developers.
Package designers work hand-in-hand with silicon process engineers, circuit designers and electrical modeling/simulation teams to ensure that a complete and functional product is delivered. New demands of increased input/output (I/O) counts, signal integrity and signaling speeds have placed packaging technology in the forefront of SoC design.
LSI Logic utilizes multi-layer organic substrates to create microstrip and stripline architectures in its flip chip packaging construction. To minimize crosstalk from high-speed differential signals, packages are optimized with 100 ohm matched length differential traces. For high speed single ended I/O's, package design can be optimized for 50 ohm trace impedance and matched length to reduce reflections and skew. Compared to typical ceramic packages, LSI Logic's lower dielectric laminate packages allow less crosstalk (see scope photo below).
Figure 10 -- Amplitude of crosstalk on a victim package lead generated by an aggressor pulse on a nearby lead
Power supply IR drop
To minimize the digital core noise caused by large currents (due to clock trees, memories, and so forth) flowing through the supply lines, larger pathways need to be created. This will minimize the resistance of the core supply lines. The power mesh IR drop analysis will dictate the width of the power metal traces. If indicated, the width can be increased as needed. The figure below shows the power mesh. Note the very wide traces. The traces running out to the peripheral I/Os are for the signal bumps while the metal in the center of the chip is for power and ground.
Figure 11 -- Example of a wide metal power and ground mesh on an ASIC
As part of the LSI Logic ASIC flow, the robustness of the power distribution is verified by analyzing the power strapping and static IR drop in the power mesh. All the nets connected to the core power supply are analyzed based on the LSI Logic circuit power models. Using simulation vectors, the possible current flowing in the power supply mesh is calculated and the results are displayed graphically.
Figure 12 -- Plot showing graphically the voltage distribution on the power mesh of an ASIC
Instantaneous voltage droop
To minimize instantaneous voltage droop (IVD) of the core power supply, power supply decoupling capacitors can be inserted on the chip. In the LSI ASIC tool flow, these are inserted automatically near large memory instances and are also placed throughout the chip where extra room is available. They can make a dramatic difference in minimizing power supply IVD or noise. Time skew can also be inserted into the clock net to help spread out the instantaneous current requirement generated by thousands of clock nodes switching simultaneously. This avoidance technique helps to reduce the requirement for on-chip decoupling capacitors.
Power supply noise improvement
The scope photo below shows the same measurement as the previous scope photo showing power supply noise on an ASIC. The measurement here was taken after signal integrity improvements were made to the device. Decoupling caps and improved power strapping helped to reduce the IVD on the core power supply from 110mV to 42mV peak-to-peak.
Figure 13 -- Noise on the digital core voltage supply of an ASIC after signal integrity enhancements, including decoupling caps and improved power strapping (42mV peak to peak)
Based on the history of many technology generations, numerous test chips and hundreds of customer ASICs, LSI Logic has created an ASIC tool flow that contains previously unmatched capabilities in terms of signal integrity analysis. The Flexstream flow makes signal integrity the rule rather than the exception and allows right first time silicon by avoiding signal integrity problems rather than fixing them.
David Chase is a Field Applications Engineer supporting High Speed Interfaces for LSI Logic in the San Francisco Bay Area. Chase began his career in ASIC technology as an analog designer and has supported ASIC technology in the field since 1992. He has held FAE positions at GEC Plessey and Symbios Logic. He joined LSI Logic as a result of the Symbios Logic acquisition in 1998.