SAN MATEO, Calif. United Microelectronics Corp. last week became the first foundry to join the X-Initiative, announcing it will accept designs using X-Architecture routing for its 0.18-, 0.15- and 0.13-micron processes. The move expands the debate over the use of diagonal wires in global routing, letting fabless semiconductor companies not just giant and well-funded integrated device manufacturers take a serious look at the technology for the first time.
The announcement is a milestone for the X program, which has steadily progressed over two years from study groups to first fabrication of masks and test patterns and then, earlier this year, to first fabrication of a working test circuit. To date, all silicon using the X-Architecture has been built at IDMs such as STMicroelectronics and Toshiba.
The X-Initiative has become a huge effort spun from a simple and very old idea. At its core is a concept that dates to the rubylith-and-Exacto days of silicon design: that the shortest path for metal to take between two contacts is a straight line, not a stairstep-shaped Manhattan route. The X-Architecture permits diagonal routes on specific higher metal layers, in theory substantially reducing the length of metal in a circuit.
As always, the devil is in the details, and problems popped up at almost every stage of manufacturing from mask data preparation to mask making and inspection, lithography and wafer processing. Only some mask-writing equipment and steppers are capable of delivering X's diagonal patterns.
Design problems exist as well. In fact, according to Aki Fujimura, chief technology officer for new-business incubation at Cadence Design Systems Inc., which is heavily involved in X development, to fully exploit X design teams must change much of their flow not just global routing but also physical-synthesis algorithms, power and timing estimates, local routing, cell placement, extraction and, eventually, cell design. This is a potential bonanza for Cadence, but worrisome to design managers.
In exchange, X offers modest improvements in power, die area and performance, although there are trade-offs among the three. Fujimura showed examples of individual designs that had been crafted using X techniques to attain up to, in once case, a 20 percent area reduction or, in another case, a 23 percent performance improvement.
UMC is in the process of running three wafer lots containing X test patterns, its first actual wafers using the architecture. Patrick Lin, chief system-on-chip architect at UMC, said the foundry is confident enough to accept designs now, based on its study of the voluminous work the initiative has done already, and intensive study of its own process.
With a major foundry available, fabless semiconductor companies may start taking a closer look at the technology. Certainly few fabless vendors could afford to ignore a substantial die area reduction with associated reductions in interconnect delay and power dissipation if it were to come essentially for free.
"There are two components to the evaluation of something like X from our point of view," said Tim Saxe, vice president of engineering at QuickLogic Corp. (Sunnyvale, Calif.). "First, does it do what they claim technically? And second, what does it do to the tool chain not just internally, but all the way out through our foundries?"
On the first point, Saxe wondered if the benefits of diagonal routing might be more available to large blocks of random logic than to a highly ordered array with programmable interconnect such as an FPGA. On the second, he expressed concerns regarding the impact of diagonal features on the foundry process.
Andrew Kahng, a professor at the University of California, San Diego, and a member of the X-Initiative technical advisory board, said the technology's benefits are largely as advertised. His research team at UCSD has constructed prototype routing tools to explore the implications of diagonal routing, and has confirmed that the technique, used in the upper interconnect layers, is able to reduce the average length of semiglobal and global routes, he said.
Kahng pointed out that this reduction triggers what he called a "'virtuous cycle," in which the reduced routing and congestion permitted a closer packing of cells, which in turn permitted further reductions in wire length. Each time the wires are shortened, signal delays, crosstalk and power dissipation into RC parasitics are all reduced as well.
"We found that, often, the overall improvement in the design is actually greater than what you would estimate by just looking at the Steiner trees with diagonal rather than orthogonal routes," Kahng said. Nevertheless, Kahng conceded, the decision to use X would result in a narrower choice of design tools.
"Certainly the tools for semiglobal and global routing have to be made available for X," Kahng said. "But there are implied needs for floor planners, extraction, power and clock routing as well."