Austin, Texas - As IBM Corp. champions statistical timing to stem the rising tide of variations in deep-submicron CMOS processes, a debate is raging over whether probabilistic approaches should indeed supplant deterministic timing methods.
At the Tau 2004 Workshop on digital timing here last week, IBM engineers reported testing the company's EinsStat statistical timing analysis tool on ASICs as large as 2.1 million gates and achieving markedly shorter run-times than are possible with the Monte Carlo optimizations used widely today. EinsStat holds out the promise of higher microprocessor performance, since designers can reduce the amount of pessimism (timing slack) in their designs, they said.
The IBM presentation set off a furious debate among the 75 timing experts present over whether deterministic timing will soon fall to the statistical approach. Among those voicing skepticism was one of IBM's own chip design managers, Carl Anderson, an IBM fellow who has led design efforts on several of the Power series of microprocessors developed within IBM's Austin Research Center.
Intel Corp. has seen similar tensions, as EDA managers pushing statistical timing clash with designers skeptical of its benefits, according to Intel timing engineers attending the workshop, organized by the IEEE and the Association for Computing Machinery.
Chandu Visweswariah, a timing expert at IBM Research in Yorktown Heights, N.Y., and Kerim Kalafala, a manager with the EDA development group at IBM Microelectronics, said the EinsStat tool piggybacks on top of EinsTimer, the "golden" sign-off timing tool that IBM has used internally for the past decade. EinsStat incurs a 40 to 50 percent increase in the total CPU cycles required to do timing runs during chip design optimization, which the presenters characterized as an acceptable overhead.
EinsStat analysis required about 18 seconds to optimize a test chip of about 3,000 gates, while a comparable Monte Carlo optimization took nearly 14 hours, IBM reported. Optimization of the 2.1 million-gate test ASIC took an hour and 10 minutes with EinsStat, IBM said.
Kalafala said because IBM is an integrated device manufacturer (IDM), it has, "under one roof, all of the resources needed" to move statistical timing into practical use. Besides the EinsStat tool, IBM must develop a set of cell models of the NAND and NOR cells, multiplexers and other basic circuit building blocks. Those models can call on measurements taken of actual devices made on IBM's newest process technology.
Chip designers have long accepted that any company's process technology will exhibit some variation in such characteristics as metal widths and oxide thickness, as well as variability in such environmental factors as power supply voltage and temperature. Deterministic, static timing analysis deals with such variations in a corner-based manner, with best-case, worst-case and normal timing delays factored in.
Today, however, two trends are converging toward a paradigm shift, Visweswariah said. First, he said, process- variability control has not kept pace with scaling, making for worsening variations in any given process. Second, Visweswariah said, "the number of independent sources of variation has gone up dramatically." Each level of metal can vary markedly, with significant disparities in interconnect delay that no longer can be ignored. Within each device family are high-threshold-voltage, low-Vt and thick- or thin-oxide versions, all of which can vary independently.
To deal with power consumption, companies offer multiple voltage islands on a chip; higher voltages are used for the most performance-sensitive circuits. These multiple power supplies can vary independently as a critical path snakes through them before reaching a latch and getting clocked.
"All of these factors are forcing us to look at timing in a fundamentally new way. That's where statistical timing comes into account," said Visweswariah. As clock and data signals race toward each other, static timing analysis requires that timing be worst-cased, setting data as slow as possible and the clock as fast as possible and then comparing the two to judge whether the timing works. "This becomes increasingly pessimistic as you have increasing sources of variation and as the amount of variability increases," Visweswariah said. The bottom line is that performance is left on the table.
Statistical timing seeks to improve the situation by providing probabilistic values, allowing best-case timing to be within a range of values that is compared with a range of values for the worst case. The result is a more nuanced approach than is possible with static timing analysis.
Visweswariah argued that the Monte Carlo approach-which works with a Spice engine to analyze variables by comparing thousands of simulated models of a NAND cell, for example-will take too much time as process variables increase.
Many of the researchers here agreed that statistical timing eventually will come into play to reduce the excessive conservatism that is built into design timing now. How soon that will happen, however, is open to debate. In an invited speech, IBM's Anderson said statistical timing is "not on my wish list" for new tools. More important problems face a processor design team, he said, including "horrible" increases in wire resistance across a chip and the need for a common tool database. Most important, he said, tools must work faster.
Statistical timing analysis "does nothing to solve any of these problems," Anderson said, adding that designers prefer to work with the best models they can obtain, achieve first silicon and then fix problems as the design is iterated.
"Designing a microprocessor is a huge job, and changing [the design methodology] is like turning an oil tanker," Anderson said. "Almost every week someone comes into my office with a new [tool] idea, and a manager has to be able to say 'No'; that is key to getting a processor out on schedule."
In a brief interview following his speech, Anderson said he has discussed the use of statistical timing but is reserving judgment for now. "We need a very good reason to change something. What we do now is [run] a couple of spins of the silicon and then go in and fix things."
Intel participants at the workshop suggest a similar lack of consensus existed within their ranks. Tanay Karnik, an EDA engineer working in the circuit research lab at Intel's Hillsboro, Ore., facility, presented an Intel paper on statistical timing.
As scaling proceeds to 65 nanometers and beyond, Karnik said, "the systematic variations are something that we can tolerate in design, but the random variations are increasing. If we have variation-tolerant designs, we will win in terms of frequency. In my opinion, we are going to see a major shift from deterministic [timing] to probable and statistical timing for the design of high-performance circuits."
But Noel Menezes, manager of performance verification at Intel's strategic CAD Lab in Hillsboro, said "there is a healthy skepticism on the part of the designers at Intel" about the value of statistical timing and the added run-times it may entail. "There are good reasons for that reluctance, in my opinion," Menezes said, noting that Intel is researching statistical timing and has even tried the approach experimentally.
"What statistical timing does is describe the sigma, the degree of variation, in a process. What our designers are telling us is that we have to do a better job of figuring out the mean, i.e., the average point in the process that can be factored into existing timing tools. Until we figure out the mean, we can't get the slop out of the design," Menezes said.
EDA vendors also weighed in on the controversy. "The industry needs to do statistical timing; only the methods are in doubt," argued Lou Scheffer, a research fellow at Cadence Design Systems Inc. "If you are trying to do it at the cell model only, that puts a lot of demand for access to data about the variations on the cell models."
In that sense, an IDM may have an earlier chance to implement statistical timing, given the "all under one roof" argument. But Scheffer noted that gaining access to fab variation information is not easy, even within IBM. And cell models, already several gigabytes in size, would become much larger if several different forms of process variability are taken into account.
"We may end up using cell-level analysis to pick out the worst critical paths, and then go ahead with transistor-level variability. I applaud IBM's effort to do statistical timing analysis, but I know the designers worry about time-to-market being affected," Scheffer said.
"There are many substantial timing challenges at 65 nm, of which statistical timing analysis represents only one portion," Rajiv Maheshwary, senior director of marketing for static time, power and extraction at Synopsys Inc., told EE Times. "An accurate timing-analysis solution must also provide Spice-accurate cell and interconnect delay calculation, handle dynamic operation of the chip and model parametric effects caused by process variations."
Dynamic operations through multiscenario technology, enhancing delay calculation, and modeling parametric variations using statistical techniques are "three key innovation areas" on the Synopsys road map, Maheshwary said.