As system design companies deal with the trials of today's economic environment, they face the dual challenges of finding ways to improve the efficiency of their product development and manufacturing processes, while at the same time managing the increasing complexity of those products. These business factors are creating the need for more efficient implementation of high density, high pin-count FPGAs, ASICs, and ICs on printed circuit boards (PCBs) and new workflow methodologies that allow companies to meet time-to-market and design performance objectives.
The need for more efficient processes is especially relevant when we consider the recent advances in FPGA density and performance that are spurring an exponential growth in FPGA design starts. FPGAs are appearing in an increasing number of applications, driving the need for FPGA and PCB design tool integration.
For example, a PCB may contain several high pin-count (1,500 to 2,000) FPGAs that are being designed at the same time as the PCB in order to meet aggressive time-to-market goals. Pin-out changes in the FPGA package must be continually reflected into the PCB schematic and layout design database. High-speed signal integrity analysis tools for the PCB must have access to verification models for I/O drivers and receivers. Routing of the PCB for either completion, or to meet high-speed timing, may also require pin-out changes to the FPGA.
A prime example of this dual track design process would be the design of several FPGAs for a single PCB. The design of the FPGA might include tools from both an EDA supplier as well as the FPGA vendor. The design of the PCB would include tools from an EDA supplier, not necessarily the same as the FPGA tools supplier.
The first problem is to simply reflect the results of the FPGA place and route tools into the schematic and PCB layout tools. For a 1,500+ pin FPGA, this process could take over a week if done manually. A large FPGA would require a process in which the symbol was functionally broken up (fractured) in order to fit on even the largest schematic sheet. As the FPGA design process continues, the pin-outs change (typically 4-6 times) and without a totally automated FPGA tool to PCB schematic symbol and geometry process, design schedules would be missed.
Unfortunately, the design of the FPGA is not solely under the control of the FPGA designer. As the FPGAs are placed and routed on the PCB, timing and delay tuning of interconnect nets may require changes to the pin-out assignments of the FPGA. With a PCB design system that understands the pin swapping and driver rules of the FPGA, these pin changes can be made in the PCB environment and then automatically reflected back to the FPGA tools. If the PCB tools don't have the FPGA rules, this can become a very iterative and time consuming process.
To ensure proper performance, a high-speed verification must be performed which includes the exact routing on the PCB. With the multi-gigabit speeds now commonplace on FPGAs, design kits, supplied by the FPGA vendor, must contain accurate IBIS, Spice or VHDL-AMS models. With these models, and PCB verification tools that can analyze in the GHz ranges, the design can be verified for signal integrity and performance.
The bottom line is that electronics companies require tight, bi-directional integration of their FPGA tools and their PCB design tools as well as close cooperation between their EDA and FPGA suppliers. With this integration and cooperation, time-to-market and performance goals can be met. Without it, the ever-increasing complexity of systems design will stall the process and ultimately limit or eliminate the electronics company's profits.
John Isaac is a market development director for the Mentor Graphics Systems Design Division.