SANTA CRUZ, Calif. Plugging a major gap that has made it difficult for chip designers and EDA vendors to embrace the OpenAccess database, Hewlett-Packard and Cadence Design Systems have donated a Verilog reader/writer to the OpenAccess Coalition. Available for free download, it lets designers exchange netlist information directly with OpenAccess.
When Hewlett-Packard developed an OpenAccess-based design flow for a 90 nm chip design last year, that company had to write its own Verilog reader and writer in order to populate the database and interface with tools not available on OpenAccess. But that work has apparently had a positive outcome, leading to the development of a Verilog reader/writer kit available to anyone.
The kit consists of mapping documents, source code, binaries, user documentation, and unit tests. The translators read or write Verilog to, or from, the OpenAccess database according to the mapping documents. Those documents describe the correspondence between Verilog syntax, as defined by the IEEE 1995 and 2001 standards, and OpenAccess database objects and API.
The Verilog reader kit, including source code and executables, is available now at the OpenEDA web site. The Verilog writer mapping document and associated user documentation will be available in May 2004.