You've heard this before engineers grumbling to their managers and nagging the electronic design automation (EDA) vendors to help them move up the levels of abstraction. Engineers just can't design a large chip one transistor at a time. They have to have quantities of scale to help pull off a large project.
Engineers are moving quickly to higher levels of abstraction, from register transfer level (RTL) to the behavioral and specification levels. As a result, the sphere of influence is moving upstream to the specification level and offers up a whole new set of engineering challenges. Not the least of which is integration and analysis.
This should come as no surprise. Five million gate chips just can't be designed from scratch today. We're entering into an era where more engineers are buying intellectual property (IP) to do big, complex systems on chips (SoCs). In fact, engineering teams buy or reuse between 50 to 70 percent of each design. The "Design-design-design" paradigm has become "Reuse-license-integrate-design" reality.
Just consider: Customer-owned tooling (COT) projects have 30 percent of die area in memories. Project teams purchase standard cells and I/O cells. Processor and digital signal processor (DSP) design is relegated to only a few specialty companies. Numerous vendors supply IP peripherals and analog IP. Scouring the World Wide Web has become the only means to integrate the design chain into engineering projects.
And, the preferred mode of early chip estimation and analysis is still the financial modeling application software spreadsheets. Engineers continue to use them to analyze design estimates and forecasting, and for project management. That's because no single system has been capable of giving chip architects, engineers and managers timely information about how a design will behave in a production process, starting from the specification level.
Not much has changed in 30 years. Specifications for complex chip designs still start on a napkin or a piece of paper. They are refined on whiteboards, in documents or in presentation systems. These crude specifications are then transferred to spreadsheets for estimation.
Getting information on the right IP, behavior of standard cell library, and features of memories represent a massive data collection challenge for managers and architects. Often, there is only a modicum of understanding of what can be realistically expected of a design in production.
Inconceivably, multi-million dollar projects have been scrapped after six months when the management team realized the design specified on a napkin would produce a bad yield, burn the package or worse. Spreadsheet analysis is no longer sufficient. Early initial guesses often become nails in the project coffin.
These challenges for accurate early chip estimation and analysis are many and may appear daunting, but they not insurmountable. What's needed, then, are EDA tools to manage the information and become vital to this move to the specification level.
In this new sphere of influence, specification-level chip estimation will become an umbrella for the EDA process and will help engineers launch into other EDA tools. Electronic specification development for SoCs with full knowledge of the chip supply chain of libraries, memories and IP is coming. A good estimation platform can enable an engineer's spec to get transformed into the information that can be fed through the semiconductor supply chain.
At the core of any engineering project is the need to get the electronic specification document correct and accurate. As more engineers move to designing at the specification level, the need for early and accurate chip estimation and analysis software becomes acute. They can't be expected to rely on outmoded spreadsheet estimates. As with other aspects of our lives, chip design needs to have constant, updated and accurate data so it can meet the challenges of today's competitive, price-sensitive market.
J. George Janac is Chief Executive Officer (CEO) and Chairman of
Giga Scale Integration Corporation.