SAN JOSE, Calif. System-level tool vendor CoWare Inc. has added graphics-based front-end design software and other features to the System Designer tool of ConvergenSC, its family of SystemC-based system-on-chip design and verification products.
Mark Milligan, vice president of marketing at CoWare, said the graphical front end is an improvement for ConvergenSC users, who previously manually created an SoC architecture by combining various intellectual property and SystemC models, then inputting the architecture into CoWare's SystemC simulator.
The graphical front end of the Advanced System Designer tool in the 2004.1 release of ConvergenSC lets users more easily design architectures and partition hardware and software before going to verification, he said.
With the front end, ConvergenSC supports top-down, platform-based design as well, he said. "Typically system designers want to use a top-down design approach, and semiconductor customers use a platform-based approach," he said. "The new software allows users to very quickly graphically create an SoC architecture. It allows users to take an application and partition it into what's going to be hardware and what's going to be software."
Users feed a SystemC description of functional specifications, cores or a platform composed of several cores from the ConvergenSC Model Library into the ConvergenSC product.
"Once you have those in the graphical tool, you can drag blocks out of the functional spec and place them on the processor or on the bus model," said Pete Hardee, director of product marketing at CoWare. Interface synthesis then creates low-level software drivers on the processor side that allow the software to talk to hardware.
"It also creates the interface for you on the transaction-level bus model for any hardware you placed on the bus," Hardee said.
The Interface Synthesis in the tool's current release automatically generates an RTL implementation for the interconnect or on-chip bus from the transaction-level platform model, freeing hardware engineers to concentrate on designing IP blocks attached to the on-chip bus, Hardee said.
Designers can then proceed with their work using the traditional ConvergenSC flow: running the design through SystemC simulation and analysis until they converge on an architecture that meets their requirements, then using the Advanced System Designer to generate RTL for the traditional hardware design process.
Beyond the addition of graphical-based design and partitioning to the front end of the tool, ConvergenSC System Designer's debugger supports multithreaded designs. And its analysis tool has new windows or views that let users observe the design dynamically during simulation.
Multithreading lets the user "more easily keep track of what is going on in concurrent threads of the design," said Hardee. "We think users will benefit because they can now use a debugger that was designed for hardware rather than software."
With the 2004.1 release of ConvergenSC, System Designer now has more than 30 analysis views, Hardee said. "Rather than just enable people to do all the monitoring they need for analysis and look at these views after simulation has run, users can hook up views while simulation is running," he said.
ConvergenSC also includes an interface to mixed-language simulation with Mentor Graphics Corp.'s ModelSim and Verisity Ltd.'s Specman Elite. The tool previously provided links to the respective verification environments of Cadence Design Systems Inc. and Synopsys Inc.
All of the new features are available in ConvergenSC's Advanced System Designer software, which starts at $60,000. With the exception of the graphical-based design and partitioning software, all of the features are included in the base configuration of System Designer, which starts at $35,000.