SANTA CRUZ, Calif. When Agilent Technologies Inc.'s ASIC products division first moved from 130- to 90-nanometer chip design, it got a nasty surprise. "Signal integrity," said Jay McDougal, microprocessor design methodology manager at Agilent, "was really an order of magnitude worse."
McDougal's experience seems to track with that of other users and matches what EDA vendor representatives are saying. Such problems as crosstalk-induced delays, crosstalk-induced glitches and power noise due to voltage drop are all accelerated at 90 nm, making design closure more difficult.
While a number of existing and new EDA tools aim at these problems, the real solution lies more in the area of methodology and education, some observers say. Designers need to allow more time for signal-integrity closure, develop a better understanding of the issues and adopt signal-integrity avoidance techniques as well as after-the-fact analysis.
McDougal's 90-nm design used a fairly conventional flow: Synopsys Inc.'s logic synthesis, Cadence Design Systems Inc.'s physical design and both Synopsys' PrimeTime-SI and Cadence's CeltIC for crosstalk analysis. Difficulties, he said, included crosstalk-induced delay and crosstalk-induced signal transition.
"We were seeing a 10 percent, or maybe even 20 percent, timing hit from signal integrity," he said. "For transition times, some paths took 100 percent hits." Signal-integrity-driven routing is mandatory, McDougal said.
At Toshiba Corp., which has done more than 10 tapeouts at 90 nm, the biggest surprise in moving from 130 nm was "design changes caused by signal integrity," said Takashi Yoshimori, technology executive for system-on-chip design. What's needed, he said, is a more accurate analysis of signal integrity and the delay variations it causes. Toshiba currently uses CeltIC for crosstalk analysis and Cadence's VoltageStorm SoC for IR drop analysis.
Raminderpal Singh, senior engineering manager at IBM Corp., agreed that signal integrity has become a significant and surprising problem at 90 nm. Part of his job is helping 90-nm customer designs get through IBM's fabs.
"As people push the density, and push the frequency, and voltage goes down, you just have a lot more happening and a lot less to live with," he said. "A whole series of effects becomes very real."
Singh said that the primary problem he sees is not so much crosstalk, but power distribution noise. "I'm not saying [crosstalk] is not happening; I'm just not seeing it as dominant as power distribution issues," he said. "Maybe it's because people can design away from crosstalk. What I hear about is the issues they can't fix."
The effects of power bounce and voltage drop are one of those issues. "If you have power bounce going on, and that's a function of power distribution and noise, you're going to see delays and timing effects," he said. "It's probably a big cause of functional mishaps and failures." Interconnect extraction can find problems, but is harder at 90 nm, he noted.
"For power distribution and power noise, the market seems to require more dynamic analysis these days," Singh added. "When clocks start generating noise, it's more dynamic than static."
Signal integrity for nanometer ICs is a major focus at the Electronic Design Processes 2004 workshop convening this week in Monterey, Calif. Juan-Antonio Carballo, research staff member at IBM and conference chair, noted that a conference keynote addresses this issue. "The focus seems to be migrating to crosstalk and especially Vdd/ground issues " I'd say anything related to how low voltages amplify these effects," he said.
Down to the wire
EDA vendor representatives feel their customers' pain. Some process-related issues make signal integrity worse at 90 nm, said Jim McCanny, marketing group director for timing and signal integrity at Cadence. At 130 nm, he said, 75 percent of capacitance may come from adjacent wires rather than ground. At 90 nm, this goes up to 80 percent. That may not sound like much of a change, but there's more.
"Resistance went up 30 to 40 percent from 130 to 90 nm," McCanny said. "Total noise issues really relate to resistance and capacitance. As resistance goes up, the ability of the driver to drive the lines effectively goes down, so the RC changes."
The other problem is the drive to low power, which results in multiple-voltage designs, dynamic voltage scaling and different voltage "islands." All affect noise and delay. For example, these days designers are using a combination of low-Vt and high-Vt cells to combat leakage current, swapping in low-Vt cells when performance is the priority, and high-Vt cells to keep leakage current down.
"The decisions people make to control leakage are making designs more susceptible to crosstalk and IR drop," said Vinod Kariat, R&D group director for timing and signal integrity at Cadence. "If a high-Vt cell is driving a low-Vt cell, the high-Vt cell is less able to defend against crosstalk, and the low-Vt cell is more likely to propagate."
Unlike Singh, McCanny sees crosstalk as the No. 1 signal-integrity problem at 90 nm, followed by the complications of low-power design. What's important, he said, is crosstalk avoidance during routing, not just analysis and repair.
Synopsys customers are running into crosstalk-induced delays, crosstalk-induced functional problems such as glitches and voltage drop, said Rajiv Maheshwary, senior director of marketing for Synopsys' implementation group. "You have taller and thinner wire, and they're getting a lot closer, so you have increased coupling capacitance," he noted.
Further, Maheshwary said, people are doing aggressive power management of voltage grids at 90 nm, which, along with increased current density, can exacerbate on-chip and package inductance. Voltage drop, he noted, needs to be looked at dynamically rather than statically.
At 90 nm, Maheshwary said, what's important is avoidance throughout the implementation flow. Designers need to consider noise during placement, he said, and pay a lot more attention to clocks during routing, since clocks are becoming aggressors on nets.
Both Cadence's CeltIC and Synopsys' PrimeTime-SI are crosstalk analysis tools. The two have become highly competitive in the 90-nm market.
Magma Design Automation Inc. sees crosstalk as the main signal-integrity problem at 90 nm and tackles that with its Blast Noise tool, said Emre Tuncer, director of product marketing. In addition to analysis, he said, Blast Noise offers optimization, sizing and buffering. He said it could replace CeltIC or PrimeTime-SI, but acknowledged that many customers still run one of those as a sanity check.
Sequence Design Inc. offers Physical Studio, which analyzes not only crosstalk but also timing, electromigration and power. It has a dynamic voltage-drop analysis capability. "Voltage drop affects delay, which will come back and change your timing number," said Vinay Srinivas, director of R&D at Sequence. "We feel all this has got to be done in a single electrical analysis engine."
If a given instance in a design has a lower supply voltage due to voltage drop, Srinivas noted, it may respond to a glitch very differently than it would at the nominal supply voltage. He also noted that the use of high-Vt cells has a profound impact on signal integrity and noise.
Smaller, newer EDA vendors are coming forth with products that can analyze the effects of power on signal integrity. Nassda Corp., for example, introduced a "power network reliability" module for its HSIMplus platform this month. It provides a dynamic voltage-drop analysis capability. Apache Design Solutions Inc.'s Tomahawk-SDL is another dynamic voltage-drop analysis tool that can look at impacts on clock skew and timing.
But tools alone aren't the answer, some say. "The biggest challenge is having the foundry knowledge for how to implement the tools," said IBM's Singh. "We see people being successful when they set up the right tools in the right manner based on the process, and the design is careful about the ground rules."
At 90 nm, said Cadence's Kariat, designers just need to make signal integrity more of a priority. "They allocate the same amount of time they spent at 130 nm, and then they're taken by surprise, often when they're very close to tapeout under pressure," he said. "They don't plan enough time at the end."