SANTA CLARA, Calif. An EDA startup here promises to give ASIC, structured-ASIC and FPGA designers new ways to speed code through synthesis and, ultimately, all of chip design.
The startup, Blue Pearl Software Inc., said its upcoming technology will identify and fix functional and design-for-test (DFT) errors in RTL code, locate false paths and automatically generate timing constraints for synthesis.
Blue Pearl merges the marketing and sales expertise of president and CEO Ellis Smith with the tool prowess of Prab Varma, the company's vice president of engineering and CTO. Varma, the founder and CEO of Veritable Inc., teamed earlier this year with Smith to expand Veritable's technology into new tool markets, addressing what the company calls RTL closure.
Now, Veritable's entire staff has joined Blue Pearl, which has 16 employees. Smith said Blue Pearl will offer technology that tackles the number of iterations spent in a design cycle at the register-transfer level. "It resolves problems of functionality, timing and DFT closure before going to synthesis," said Smith, who has also been CEO at both TransEDA and Exemplar Logic.
Blue Pearl still offers and supports Veritable's Verity-Check RTL-code static property checker but is using the Verity-Check engine as the basis for three new products, Smith said.
"Blue Pearl is addressing functional closure, timing closure and DFT closure using Veritable technology in symbolic simulation and state-space exploration," Varma said. "Blue Pearl is addressing a much larger problem than Veritable. A significant amount of time is spent trying to achieve RTL closure. We are addressing a number of those issues that delay designs at the RT level so users don't have to make as many iterations from gates back to RTL."
One upcoming Blue Pearl tool will address timing. "Often the paths that are being identified by timing analysis are false, and users spend a lot of time trying to figure out if they are true or false and end up overconstraining the design," said Varma. "As a result [designers] end up leaving timing on the table. Our tool identifies those false paths, which eliminates overconstraining the design and results in performance improvements."
Blue Pearl's tool will automatically generate SDC-format timing constraints, Varma said, noting that generating and verifying them has also traditionally been a manual task.
A second Blue Pearl product will identify DFT rule violation in RTL code.
"For DFT closure, we do a symbolic simulation-based, procedure-based functional analysis as well as structural analysis," said Smith.
"DFT analysis is typically done after synthesis at the gate level," Varma said. "Typically you set up test procedures and check that those rules are correct. We move that procedure to the RT level. Before you get to gates, you can write test procedures to verify your controller operation." Varma said the tool identifies test violations and displays the origin of the issue in the user's RT code
Blue Pearl's third product, the one most closely associated with Verity-Check, will verify intended design behavior. It will find functional failures, identify where they occur in the code and generate a testbench or waveform displaying what is causing the failure, said Varma.
Smith said all three products will be targeted at ASIC and structured-ASIC design markets, while the timing-closure tool will likely be attractive to FPGA designers, since the tool helps users locate and eliminate false paths in their design, a common, nasty issue in FPGA design. He said that users will be able to license all three tools separately or together in a single environment.
What's unique about Blue Pearl, Smith said, is that just about everyone in the company has previously worked together. Varma, for example, worked at CrossCheck Technology, which was headed by Smith.
Privately funded by U.S. and Asian investors,the company has enough cash to see it through a third-quarter product introduction, Smith said.
The company has recruited Athanasios (A.K.) Kalekos, formerly a general partner with Telos Ventures and senior vice president with Cadence Design Systems Inc., for its board of directors.
The company's technical advisers include Michael Bohm, vice president of engineering and CTO of AccelChip, and Mark Fuccio, CEO of Tactics Inc., who has held management positions with Philips Labs, Trilogy Systems, Daisy Systems and Silicon Graphics.
Blue Pearl will show its tools in a demo suite at the 41st Design Automation Conference in San Diego next month.