SANTA CRUZ, Calif. Setting the stage for what critics fear could result in a Verilog language schism, the Accellera standards organization voted Thursday (May 27) to donate SystemVerilog 3.1a to a new IEEE working group rather than the IEEE 1364 working group that's responsible for the standardization of Verilog. The result will be two separate Verilog standardization efforts within the IEEE.
Accellera will donate the language to a new SystemVerilog study group within the IEEE Standards Association's (IEEE-SA) recently-formed Corporate Advisory Group (CAG), as opposed to the IEEE 1364 committee, which operates under the IEEE Design Automation Standards Committee (DASC). The study group has been formed and is issuing a project authorization request (PAR) under the IEEE 1800 label. Accellera has asked for a liaison to be appointed between IEEE 1364 and IEEE 1800.
The reason, said Accellera chairman Dennis Brophy, is that the CAG offers a faster path to standardization. It has a policy of one vote per company, as opposed to the IEEE 1364 policy of one vote per participant. "I think we'll have a strong standard in place sooner than something that might take years to evolve," he said.
What this means, however, is that two different Verilog standardization efforts will be ongoing. One is IEEE 1364-2005, an upcoming revision of the IEEE 1364-2001 Verilog standard, while the other will be IEEE 1800. SystemVerilog backers Synopsys and Mentor Graphics support Accellera's decision, while representatives of Cadence Design Systems and Verisity, which have strongly supported the IEEE 1364, are critical.
"I think it's a step backwards for the industry," said Mike McNamara, IEEE 1364 chair and senior vice president at Verisity. Speaking for himself rather than the IEEE, McNamara said the possibility of a language schism is very real. "There's no structure in place to prevent that," he said. "I think the natural evolution will lead in that direction [schism], and it will take incredible efforts to keep that from happening."
McNamara expressed befuddlement at Accellera's decision, noting that the IEEE 1364 group has offered a number of proposals for speeding SystemVerilog standardization and even offered to change to a "one company, one vote" policy, which appears to be Accellera's primary reason for selecting the CAG.
"Accellera and the IEEE 1364 started this process three years ago to rapidly develop the standard outside the IEEE, and then take it to the IEEE 1364 for standardization," he said. "I feel like we've been engaged for three years to be married, and here we are at the altar and they're ready to marry someone else," he said.
Accellera's decision is a "complete shock," said consultant Stu Sutherland, who has been active in both the Accellera SystemVerilog committee and IEEE 1364. "Those of us who first conceived of, and dedicated three years of volunteer time and effort to define SystemVerilog, did so in order to enhance the IEEE 1364 Verilog standard," he said. "It was the stated intent of members of the Accellera SystemVerilog committee that our work be transferred to the IEEE 1364."
"I personally feel betrayed by the Accellera board of directors who either voted against transferring SystemVerilog to the IEEE 1364 standard, or who abstained from voting," Sutherland said.
Victor Berman, group director of language standards at Cadence, warned earlier this month that donating SystemVerilog to a new IEEE entity could lead to a "bifurcation" of the language. But Berman, who is both vice-chair of the DASC and an Accellera director, struck a more conciliatory tone after the Accellera vote.
"Having a single group would be easier to control than having two groups and trying to get them to work together," he said. "But the important thing is that it's going to the IEEE. I'm still not discouraged I think we can work on this and make it come out right."
The main reason for the Accellera decision, Berman confirmed, was the "one company, one vote" policy of the CAG. He noted, however, that such a policy could be adopted under the DASC as well. Otherwise, he said, there's really no difference in procedure between the IEEE 1364 group and the new SystemVerilog group that's forming now, and he expressed skepticism that the CAG approach will actually be faster.
Brophy said that user companies within Accellera were pushing for that organization to work with the new IEEE-SA CAG. "It signals a desire on their part to see work within the IEEE proceed with the same market relevance that was used to build SystemVerilog, the same speed, the same corporate involvement, and the same connection with international bodies with which to ensure adoption."
As for the IEEE 1364 group, Brophy said, "you can do the math. From 2001 to 2004, there's been limited adoption of the full [Verilog 2001] spec."
Rich Goldman, vice president of strategic market development at Synopsys, said Accellera's decision marks a "great day" for the design and verification community. "By working with the CAG, Accellera has assured the most effective, efficienit pathway to ratification," he said.
"Accellera's path in the IEEE matches the demands customers are placing on getting standards done with greater efficiency," said Robert Hum, vice president and general manager of Mentor's functional verification division.
Brophy said he doesn't believe there will be a language split. He noted that Accellera has worked with the IEEE 1364 group in the past, and that Accellera has recommended that a liaison be designated between IEEE 1364 and IEEE 1800 to ensure coordination. "We have done nothing to disrupt what the 1364 definition is," he said.
"We are a neutral platform," said Edward Rashba, manager of new technical programs for the IEEE-SA. "We don't take an industry position. Accellera has decided on a path and we'd like to make sure we accommodate that request."
Accellera has clashed with the IEEE 1364 working group in the past. Last year, after Accellera declined requests to donate SystemVerilog to the group, the IEEE 1364 group forged ahead with its own plans for Verilog 2005. Just prior to last year's Design Automation Conference, Brophy called the group a "rogue IEEE operation."
McNamara noted, however, that at the engineering level, Accellera and the IEEE 1364 have worked well together, with many members involved in both groups.
Now that the SystemVerilog study group has been formed, the next step is for the IEEE to review the 1800 PAR and designate an official working group, Brophy said. That should happen this summer. The standardization process may then take 6 months to two years, he said. Accellera announced its approval of SystemVerilog 3.1 earlier this week.
Meanwhile, McNamara said, the IEEE 1364 group will continue its work on Verilog 2005, much of which is actually derived from SystemVerilog. "We offered to meet Accellera in all the directions we thought might be useful to them," he said. "It's a sad day when we can't collaborate."