SAN JOSE, Calif. Last September's partnership between CoWare Inc. and Cadence Design Systems Inc. has yielded its first fruits, as the companies are this week introducing a new co-developed flow they claim will allow users of CoWare's ConvergenSC SystemC-based prototyping system to "seamlessly" transfer models built in SystemC and Verilog to Cadence's Incisive verification platform.
Last September, Cadence, amidst a reorganization period, transferred its Signal Processing Workstation (SPW) technology and supporting R&D and sales folks to CoWare, took a minority stake in company, and promised to collaborate with CoWare on sales and flow development.
"One of the major milestones we set back in September was to bring together CoWare's ESL environment with Cadence's Incisive verification platform," said Mitch Weaver, Systems and Functional Verification Division at Cadence. "We did what we said we were going to do."
In the collaboration, the companies have each ensured their respective tool flows support a common simulation kernel and compiler that facilitate the transfer of models built mostly with SystemC and some Verilog between the two companies' environments.
Mark Milligan, vice president of marketing at CoWare, said the collaborative work will allow users to create a model in SystemC that can be referenced at every step of the functional verification process.
Typically, architects create a behavioral model in SystemC to decide how they would like their system-on-chip (SoC) to behave, but that model can't be used at the RT level.
This means the verification engineers must create an HDL version of the entire or more likely blocks that compose the behavioral model of the SoC. Similarly, embedded designers must wait until the behavioral level model is proven functionally correct in HDL and then use the HDL version of the model, which is slow, or wait until a refined SystemC model is generated.
"What we've added here is the ability to capture knowledge at the [transaction level model] level or higher at a programmer's level, and use that to drive the verification process downstream using a known-good system model," said Milligan. "What we've delivered there is a way to connect the SystemC model into various types of models we've created as you refine the design through RTL and on down."
The flow, claim the companies, can reduce overall verification time by up to 50 percent.
Milligan said with the unified flow, system architects can explore the design space in ConvergenSC and determine the optimal system architecture for the SoC.
Using SystemC transaction level models (TLM), which boast a simulation speed greater than 10,000 times faster than HDL simulation, the architecture is evaluated using realistic system scenarios with software. The SystemC model and ConvergenSC software analysis is also used by software developers to validate and optimize embedded software early in the design process.
Once validated, said Weaver, the SystemC model becomes a functional virtual prototype (FVP) with an embedded software testbench. Verification engineers use ConvergenSC technology to reconfigure the FVP as a heterogeneous model. This heterogeneous model in the Incisive platform allows the verification engineer to re-use the knowledge captured in the system to verify the RTL.
Along with the common kernel, the two companies boast that they've put together the world's largest SystemC model library which is now available for use with the Incisive platform for verification. And the ConvergenSC Model Library of SystemC processor support packages (PSPs) and bus libraries now simulate in Incisive as well as in ConvergenSC.
ConvergenSC also provides a graphical platform-based design environment with automated TLM-to-RTL transactor generation for rapid reconfiguration of mixed SystemC/HDL "FVPs" using the ConvergenSC Model Library and user RTL, and export of the SystemC/HDL "FVP" netlist to ConvergenSC and the Incisive platform.
The companies have also tailored ConvergenSC and Incisive technologies. ConvergenSC supports SystemC threads and Incisive has a unified source-level debugging environment for SystemC, Verilog, and VHDL.
The collaborative functionality is available in Cadence Incisive 5.3 and CoWare ConvergenSC 2004.1, both available now.