SAN JOSE, Calif. Adding a proverbial tiara to its Miss Univers line of hardware/software co-verification tools, Adveda Inc. is introducing this week a model generator simulation add-on that places a SystemC or PLI wrapper around RTL code so Adveda's fast models can be used with established top-down and bottom-up verification environments.
Adveda's co-verification solution includes an RTL cycle accurate simulator and an instruction set simulator (ISS) both running off a single kernel for speedy hardware/software co-verification.
But the previous version did not facilitate the use of Adveda models in third-party verification flows. The new Univers Modeler solves this problem.
"We've built a wrapper around our RTL simulator to be able to accommodate people who do not want to change anything in their design flow," said Cor Schepens, Adveda's CEO, noting that the PLI wrapper will allow users to plug in Adveda models to their traditional bottom up verification flows, while the SystemC wrapper accommodates those using the newer SystemC top down flow.
For users of the new SystemC flow, Univers Modeler takes the original RTL code and converts it automatically to a cycle-accurate simulation model at a higher level of abstraction, wrapped in SystemC. The company claims the generated model will run faster than an RTL simulation, similar to the speed reached with manually-written SystemC models.
"There are a lot of people painstakingly writing SystemC models by hand," said Schepens. "This tool essentially automates model generation for them."
The Univers Modeler can also wrap these models with a PLI interface, allowing the models to be used within existing RTL simulators. It handles the full synthesizable RTL syntax, including multiple asynchronous clocks, asynchronous resets as well as tri-state signals, said Schepens. The first production release supports VHDL.