SAN DIEGO, Calif. A proposal for a phased, coordinated implementation of SystemVerilog took some heat at a Design Automation Conference panel Wednesday (June 9), as proponents squared off against critics who say the proposal is an attempt to delay language implementation. Accellera's recent decision to seek a separate IEEE standard also drew controversy.
The panel, convened by Accellera, was entitled "What is the best way to leverage SystemVerilog 3.1a?" In addition to the discussion about phased implementation, panelists heard a proposal for a free SystemVerilog reference simulator, and largely dismissed it as unrealistic.
Last month, five EDA vendors announced a proposal for a "SystemVerilog implementation working group" that will promote a phased, coordinated implementation of SystemVerilog design and assertion constructs. The vendors included Cadence Design Systems, Verisity, Magma Design Automation, 0-In Design Automation and Novas Software.
The proposal was immediately dismissed by Mentor Graphics and Synopsys, who are further along in SystemVerilog implementation, as an attempt to slow things down by vendors who are trying to catch up. Accellera representatives also expressed skepticism.
The controversy resurfaced at the Accellera panel as an audience member, consultant Cliff Cummings, rose to say the coordinated implementation proposal "sounds like de-cellera."
"I see two companies moving full steam. I see phased implementation as a way of making sure they don't go too fast," Cummings said, asking panelists for their opinions.
"I believe it is up to the user community to define what subset they want to use, not the vendors," replied Brian Bailey, chief technologist for Mentor Graphics' design verification and test division. "We have to provide the whole thing."
Victor Berman, group director for language standards at Cadence, said phased implementation isn't an attempt to slow down anything. "We want to do the whole language, but we want to make sure it's done in an organized way so people understand what the language means," he said.
"The reality is that there's going to be a phased implementation. The only question is whether it's coordinated or not," Berman said. Those who want to charge ahead, he said, are taking a "wild west approach."
Dave Kelf, vice president of marketing at Novas Software, also defended the phased implementation proposal. "If tools implement different parts of the language at different times, it means users can't use any part of the language until it's all implemented," he said. "With a phased approach, the [SystemVerilog] methodology will be adopted much more quickly."
Consultant Stu Sutherland, who supports the phased implementation proposal, rose from the audience to ask Mentor and Synopsys representatives how they defined the phases of SystemVerilog they're currently implementing.
Bailey responded that Mentor is taking discrete chunks of the language, such as design constructs and assertions, and rolling them out as they're completed. The company is picking areas of greatest user demand, he said.
Phil Moorby, Synopsys scientist, noted that nobody is going to implement all 1,000 pages in the SystemVerilog Language Reference Manual instantly. "We listen to what customers need," he said. "They don't care about every letter in the LRM, they care that what we give them works."
A chip designer in the audience had harsh words for the phased implementation proposal. "Synopsys and Mentor both have a chance to produce a golden reference simulator, and I think Cadence is desperately trying to catch up," he said. "I think it's harmful to the design community. We want tools and we want them now. I'm happy about what Synopsys and Mentor are doing."
But this designer also expressed disdain about Accellera's decision to donate SystemVerilog 3.la to a new IEEE working group and bypass the IEEE 1364 committee, a decision supported by Synopsys and Mentor. "One way to slow the adoption of SystemVerilog is to end up with two competing standards," he said. "This is a fairly desperate situation."
"My feeling is that it should be done in a single working group," said Berman, an Accellera director who voted to donate SystemVerilog to the IEEE 1364 group.
Novas' Kelf said he could see both sides. "My personal opinion is that two standards would be bad," he said. "But I think people didn't want to muck with [SystemVerilog], wanted to get through the process as soon as possible."
Karen Bartleson, director of quality and interoperability at Synopsys, spoke from the audience to note that all of the user representatives on the Accellera board voted to take SystemVerilog to a new working group under the IEEE's corporate standards program. "There was overwhelming user demand that they wanted the standard and they wanted it now," she said.
Panelist Jerry Kaczynski, manager of Aldec's advanced product group, suggested that a free SystemVerilog simulator that users could download would help speed language adoption. Other panelists said it's a good idea, but it's unlikely anyone will pay for it.
But Kaczynski had another proposal that may prove more practical. "Let's bury the hatchet. We don't need another language war," he said. "Let's concentrate on implementing SystemVerilog."