As nanometer process technologies invade the world of communications system designers, a number of increasingly exhibited effects impact and require advanced modeling support. In the timing domain, cell delays are shrinking while the stable operating regions for these cells are getting tighter. Power modeling must capture and convey the increasing leakage currents and increasing number of hidden power sources the suck the life out of batteries and degrade the lifespan of circuits.
Dropping voltages are one way to save power supply, but that leads to a greater sensitivity to rail voltage variations and smaller margins for switching noise. Sources of switching noise are increasing with the increased capacitive cross-coupling due to tighter line dimensions and the relative increase in sidewall capacitance.
In the face of these trends in nanometer electrical effects, design teams face other significant challenges. These teams, and the organizations that support them, must analyze and manage far more data for increasingly complex communications system-on-chip (SoC) designs. They must do so over increasingly shorter design cycles to meet company critical time-to-market requirements.
In addition, they probably have to do so with tighter budgets and with smaller staffs that now are stretched beyond their primary domain expertise. As critical as accurate modeling is for nanometer effects, so also is an effective characterization and modeling solution that will comprehend and address all of these critical areas.
Total power is growing exponentially with each process generation. This total power includes both dynamic and static power. Dynamic, or active, power is associated with the energy consumed while the device is in operation. Static power is the energy consumed at all times, including when the device is inactive, and is dominated by sub-threshold leakage current.
Figure 1 Trends in power across process technologies
This increased power consumption has many associated costs. For instance, increased power can force the use of more expensive packaging and system cooling mechanisms. In mobile applications that must manage battery life, power consumption becomes a competitive issue for system cost, performance and even form-factor.
Chip designers have looked at power management techniques at every level architectural tradeoffs, RTL optimizations, circuit design and process. None of the techniques developed has been a panacea; design teams use a combination of techniques at every level to optimize power consumption for a particular application.
Chip designers working at the RTL and circuit level have traditionally focused their efforts on managing dynamic power. Dynamic or switching power is proportional to CV2f at any given switching node, where C is the capacitive loading being charged at the load, V is the voltage, and f is the frequency or toggle rate of the node. Capacitive loading has naturally scaled with the scaling of process technology that has resulted in commensurate reductions in power per unit functionality; however, increased transistor density has resulted in level or increased power consumption in the chip.
Frequency continues to increase in successive process technology generations as well. Management of switching by the use of gated clocks to stop unnecessary transitions in registers and the logic cones they drive has become a commonly used technique. Architectural techniques such as the use of parallelism can be used to trade off increased area for higher throughput or reduced power at lower frequencies.
Because of the advantageous V2 impact on switching power, supply voltage scaling has been used aggressively. Shorter channel lengths aggravate the Vt roll-off effect where Vt drops rapidly with shrinking channels. This reduced Vt leads to increased sub-threshold leakage current.
Designers are forced to make performance trade-offs to improve switching power or leakage power in other ways. To the extent that these performance trade-offs can be made on non-critical timing of the design, overall performance impact can be minimized.
The leakage reduction techniques all use increased device threshold voltages to limit sub-threshold leakages currents. These approaches vary in the mechanism used to increase the threshold voltage and in the circuit placement of the high Vt devices. Many of the techniques can be implemented independently and can be combined in creative combinations to allow designers to meet application specific demands.
As a result, leakage power reduction has become a major focus in designs at 90nm and below.
Now, however, we are reaching the point where shorter channel lengths are affecting switching threshold voltages. Reduced supply voltages reduce dynamic power but aggravate leakage power.
Improving modeling we've done before
In addition to the momentum that the dual-Vt approach has seen, multi-voltage islands have begun to see increased adoption, especially for wireless communication applications. Voltage islands allow entire physical blocks or partitions to be reduced to the minimum supply voltage required to achieve timing. Operating these blocks at reduced voltages minimizes switching power during operation and to be powered down during periods of inactivity, eliminating the associated leakage power.
Designing with voltage islands requires additional care in power distribution design and island interfaces. Any additional voltage levels must be available from off-chip sources or generated with on-chip regulators. Signal interfaces between regions running on different supplies must have appropriate level converters.
If blocks are powered down, electrical "fencing" is required to prevent indeterminate state from corrupting still active blocks. In addition, powered down blocks probably need to save and restore state.
Figure 2 Voltage island powering and switching control
Design with multiple voltage islands requires a level of support in the tool flow. This support is beginning to appear in EDA tool suites. Clearly, the flow must support timing and power analysis across the multiple voltage domains simultaneously. There must be mechanisms to designate rail connections and associated supply voltage ranges for the various islands.
Since signals driving between voltage domains can be problematic, automated signal level checking is required. In addition, physical design with voltage islands adds complexity that should be provided in the floorplanning and placement tools.
One multi-voltage variation to the voltage island approach is the dual Vdd voltage cluster approach. The cluster approach is applied gate-by-gate as in the dual Vt approach rather than to entire islands. A lower supply voltage is used for non-critical paths while a higher supply voltage is used on the critical paths. The result is reduced operating power without degraded the overall performance.
Design techniques to manage standby (leakage) power
The dual Vt approach to leakage power reduction has significant industry momentum and support. An already prevalent approach to controlling leakage currents is the use of multiple Vt libraries. This approach reduces leakage power without sacrificing the timing performance of the design by using cells with increased switching voltage thresholds to replace as many of the regular threshold cells as possible without degrading timing.
The high Vt cells are identical to the low Vt cells except for processing changes. This technique takes advantage of the fact that logic off the critical path can be designed for low power, trading off timing slack. No change to the library characterization methodology is required, but the high Vt library does require a separate characterization. Modeling of the library can continue to be done with Liberty NLDM format look-up tables, and the cells can be stored in separate Liberty files.
In the dual-Vt approach, leakage current is controlled managing threshold voltages using manufacturing process techniques so that the threshold of a gate is fixed. Another approach to managing threshold voltage is the use of substrate biasing. Normally, the substrate in a digital gate is tied to GND for NMOS transistors and to Vdd for PMOS transistors. Substrate biasing is used in conjunction with process-based Vt management.
As the bias voltage for any of these devices is reduced below 0V under reverse bulk bias (RBB), Vt increases and leakage current decreases. Under forward bulk bias (FBB), Vt decreases and performance increases at the expense of leakage current.
The variable threshold or VTCMOS approach uses RBB in standby modes to manage leakage power without degrading performance. This approach assumes a low Vdd with low Vt devices are used in active mode to meet overall performance requirements, although it can be combined with dual- and multi- VDD approaches. A standby mode using RBB raises the effective Vt to block leakage current.
The requirements for the variable threshold are mostly in physical design. The architecture and layout of the library cells must modified to add discrete substrate terminals for the VBB hookup, which could be addressed as additional rail connections and handled as such in placement and routing.
Additional voltages sources must be available, and logic for the substrate bias control must be included. In the design flow, timing and power analysis calculation must account for the range of substrate biases used and the impact of variable thresholds.
Figure 3 Variable threshold (VTCMOS) scheme using substrate bias control
The high Vt sleep mode approach is a global leakage power reduction technique that requires fewer changes to the design. The design is implemented using low Vt transistors to meet high-speed performance goals. High Vt NMOS and PMOS sleep control transistors are added to form virtual supply rails (VDDV, GNDV.)
A sleep mode signal, SL, controls the operation of these high Vt transistors. In active mode, these sleep transistors function as real power and grounds with small on-resistances. In sleep mode, these transistors block the leakage currents otherwise present in the low Vt circuitry.
Figure 4 High Vt sleep mode (MTCMOS) substrate
Design requirements of the sleep control mechanism are highly application dependent, controlling decisions on partitioning of the SoC into regions that can be shut down. Design of the sleep control mechanism follows from the system level considerations. Floor plan and performance considerations govern the insertion, sizing, placement and wiring of the high VT transistors. Small allowances must be made to manage performance degradation due to the resistance of the high VT transistors.
The sleep control approach only addresses leakage of circuitry in the applicable regions during the sleep period. This approach can be combined with other switching and leakage control approaches to manage power during periods of activity.
Using models for advanced power reduction
In order to perform accurate timing and power analysis, additional library characterizations for the minimum, typical, and maximum of each voltage used in the design will be required. Designers may not know a priori what voltage(s) each partition will use, so there should be flexibility in the library support.
Most of the power reduction techniques described depend on trading off timing slack for power at the cell level. Even the block-level approaches are often combined with the cell level approaches.
Thus most designs driving for low-power, high performance applications will require analysis across multiple voltages, whether supply, bias or both. In such a case, managing NLDM look-up table models for each and every voltage point combination is unwieldy, if they are even available. Optimization of voltage levels done during the design process makes explicit characterization difficult.
Using scalable polynomial model (SPM) equations enables a characterization methodology that collects all required data to support the voltage sweeps. Because the equation allows accurate timing or power calculation at arbitrary points between measured points, design teams have the flexibility to vary voltages as needed to minimize power. A single library for each process point could contain timing and power data to support all of the described reduction techniques.
Summary and approach
Most of the advanced power reduction techniques described in the previous section use some form of voltage variation to manage switching or leakage power. In each case, timing slack and area are traded off to achieve the power reduction. One of the fundamental requirements of a design flow implementing one or more of these techniques is an improved cell model. This improved cell model must be able to represent the timing and power impact of either multiple voltage points or variable voltages used in the design simultaneously.
Robert Jones is director of strategic marketing for the Silicon Correlation Division at Magma Design Automation, Inc. The division provides characterization, modeling, and analysis products.