SANTA CLARA, Calif. The Accellera standards organization has re-elected all of its existing officers, including Dennis Brophy, who will serve as Accellera's chairman for a fifth term. Meanwhile, the organization is reporting rapid progress with SystemVerilog and the Property Specification Language (PSL), both of which are now undergoing IEEE standardization.
Brophy is director of strategic business development at Mentor Graphics. Also re-elected were Shrenik Mehta, director of ASICs and processors at Sun Microsystems, as vice-chair; Dave Kelf, vice president of marketing at Novas Software, as treasurer; and Karen Bartelson, director of interoperability at Synopsys, as secretary.
In an update meeting this week (Sept. 29), Accellera officers reviewed the current status of both SystemVerilog and Accellera. While both efforts have moved to the IEEE, many people involved in the standardization efforts are active in both Accellera and the IEEE. Among them is Victor Berman, director of Cadence Design Systems' languages and standards strategy.
While SystemVerilog is under the auspices of the IEEE's Corporate Standards Group (CAG) as IEEE P1800, and Verilog remains under control of the IEEE's Design Automation Standards Committee (DASC) as IEEE 1364, a joint oversight committee is ensuring that the language efforts remain compatible, Berman said.
Berman said that the P1800 group held its third monthly meeting in September and has made "a lot of progress." It has adopted policies and procedures, and is developing plans for administration and for sub-groups. Berman said the group's goal is to publish an IEEE SystemVerilog language reference manual (LRM) by next June's Design Automation Conference (DAC).
"It's a very aggressive schedule, but we're moving along very quickly," Berman said. "There's a lot of enthusiasm for getting this done."
Meanwhile, PSL is now a project within the IEEE CAG, designated P1850. Harry Foster, chief methodologist at Jasper Design Automation and chair of Accellera's formal verification technology committee, is interim chair of IEEE P1850. Foster said that the working group held its first meeting Sept. 28. The group wants to complete a PSL LRM by DAC 2005, he said.
In the next year, Accellera also plans to focus on standardization activities including the Open Kit IC design kit initiative and the Verilog-AMS mixed-signal language. A list of Accellera-supported technical activities is available on line.