SAN JOSE, Calif. Design tools need to become power aware, physically aware, manufacturing aware, signal integrity aware and test aware starting at the 90 nm node, said Texas Instruments Fellow, Peter Rickert, here Monday (Nov. 8) in his keynote at ICCAD 2004.
Rickert, who is member of the TI's Platform technology Development group, listed a number of issues popping up at the 90 nm process node that are likely to get worse as 65 nm processes start to come online in 2006.
Rickert said that power has become a first order concern at the 90nm node.
"The new paradigm for us as designers is that we are designing to a fixed performance instead of a fixed voltage," said Rickert. "I know what kind of voltage I want to achieve, the question is 'what kind of voltage variation can I make and still achieve the required level of performance?'"
To help with this design style, Rickert said that the EDA vendors need to develop technologies that allow designers to use multiple voltage domains and employ robust electrical rule checking. He said tools need to better understand boundary conditions and variable Vdd, as well.
Tools also need to support multiple VT libraries and need to help users apply "sleep and "drowsy modes" on logic in addition to memory higher up in the design flow, Rickert said.
Tools also need to progress in physical awareness, said Rickert, who called for EDA vendors to offer routers that optimize the use of tapered metal stacks and have better VIA planning.
Rickert said that TI has also been experimenting with Cadence's X-Architecture non-orthogonal routing technology, which allows for 45 degree routing. But he said there needs to be a supporting flow around the tool to make it viable.
Rickert also called for better that design team collaboration and management software. "I can't think of design team at TI on a single site," said Rickert.
He said he is also looking forward to statistical tools becoming commercialized, especially tools that can separate random effects from systemic effects.
He also called for interconnect centric and yield driven floorplanning and for physical tools to better understand digital effects on analog.
Rickert also called for true Design for Manufacture technologies.
He noted that the amount of design rules is exploding at finer process nodes and that the 65 nm node will require restricted design rules (RDRs).
"Clearly going into the future, geometric rules aren't going to describe the limits of manufacturing," said Rickert. "We will probably move into a realm of what can be drawn, instead of what can't be drawn, and what can be processed rather than what cannot be processed."
To get this data said Rickert will require better cooperation between customers, foundries and EDA vendors.
Signal integrity awareness has improved in the pure digital IC flow but now said Rickert the tools also have to improve in the mixed signal domain and better deal with analog and RF issues—all the signals on a system on a chip.
Finally, Rickert called for greater flexibility to insert memory BIST at the RT level in addition to or instead of at the gate level.