Almost since the inception of EDA, the grand vision of a comprehensive hardware/software design environment has tantalized designers and EDA vendors alike.
Known by many names over the past decades co-design, electronic system design automation (ESDA) and now electronic system-level (ESL) design it offered the enticing hope of specifying a system in an implementation-neutral language, pushing a button, and out would emerge the full, detailed hardware design and corresponding software. But the dream remained elusive.
Current methodologies are approaching a breaking point as ASICs and SoCs grow toward 100 million-gate chips, incorporating hundreds of pieces of intellectual property (IP). But even as complexity has increased exponentially, system teams are still relying on the traditional, iterative register transfer level (RTL) approach.
This time-consuming process involves labor-intensive, manual steps such as micro-architecture definition, creation and verification of handwritten RTL code, and area/speed optimization through RTL synthesis. The result is a widening gap between process advances in IC technology and designer productivity, creating pressure for a new approach.
EDA tools by necessity must move to a higher level of abstraction, making some level of ESL deployment inevitable. The good news is that ESL is alive and well today, but in a fundamentally different form than what was originally conceived years ago. Instead of a monolithic, comprehensive solution, ESL encompasses several categories that work to elevate different aspects of design to a higher level of abstraction.
Specifically, the ESL categories include: platform-based design, transaction-level modeling, C-based simulation, hardware/software co-verification, performance optimization, and C-based synthesis. With several solutions to choose from, designers can build the ESL environment appropriate to their needs.
Each of these categories comprises an aspect of ESL, giving the system team powerful tools for managing greater complexity. For example, using transaction-based modeling and C-based simulation, it is possible to model functional behavior without any preconceived hardware implementation or target device architecture in mind.
Engineers can quickly simulate, analyze and modify the design without being distracted with implementation details. By starting with untimed C source code, one can quickly explore different system architectures, evaluating them against key system criteria before investing effort in writing RTL.
Complementing simulation at this higher level, C-based synthesis can be used to automatically generate high-quality RTL code, eliminating the weeks/months of design work typically required in today's flow. Automating the process enables the team to develop and assess various micro-architectures with respect to a variety of design parameters. In this way, they can quickly zero in on the optimal balance of area, performance and power required for the specific application.
Once the team is satisfied with the architecture, they can use hardware/software co-verification to determine up front if the hardware will indeed work in conjunction with the software long before committing to silicon. One of the major benefits of verifying the entire system early in the development cycle is the relative ease with which system performance may be optimized by shifting functionality between the hardware and software domains to determine the best approach for achieving the desired system performance.
Since most modern design begins with a "platform" (previous generation design or a commercial design foundation), a platform-based design environment is needed to ease integration of IP blocks into buses, and to facilitate generation of diagnostics and test-benches. Co-verification and simulation can be driven by a platform-based design tool throughout the project cycle to enable true concurrent hardware and software development. By adopting a platform-based approach, software engineers can port operating systems, write drivers and develop the applications specific for the chip, so that by the time the RTL code is available the software is ready as well.
All these capabilities establish a powerful set of building blocks to be used in an ESL environment to efficiently produce highly complex, next-generation ASICs and SoCs without compromising "time to market" or performance. Solid progress is being made within each of these categories, helping ESL emerge as a reality today. EDA companies large and small are introducing innovative ESL products, leading designers closer to the dream of a truly integrated system-level flow. It's just in time to help them negotiate the demanding world of IP-based, 100 million-gate designs.
Serge Leef is general manager of Mentor Graphics' SoC division.