Many design teams are racing towards advanced processes with smaller geometries. In the ASIC world, however, it is getting increasingly harder to make money on the cutting edge of Moore's Law.
The costs of the masks and fabrication are prohibitive, and the gain in speed is not as high as it used be upon transition to the next generation in technology. Power issues and other electrical effects get worse. Furthermore, yield has been quite a significant problem for many folks trying to migrate to 90 nm and below.
When performance is critical, ASIC designers should pause to evaluate the risks of rushing to a smaller geometry, and the available alternatives. In principle, designers can extract significantly greater performance out of mature and proven processes with careful enhancements to existing tools and design flows. In particular, designers can gain additional performance at a given process node, while eliminating the risks of migration to next process node in miniaturization, through selected transistor-level optimization of designs.
With the growing size and complexity of the designs, engineers are designing at ever-higher levels of abstraction. Transistor-level circuit design is quickly becoming an art practiced by a few magicians.
While companies like Intel, Freescale and IBM are crossing multi-gigahertz barriers, the ASIC industry at large is unable to break the 400MHz barrier at the 90 nm process node. It is widely recognized that pre-characterized libraries of cells that form the bedrock of ASIC design methodologies impose serious limitations on the design process in terms of lengthened design cycle time, increased design cost, and reduced quality of the final design.
The solution lies in broadening designers' understanding of the transistors and the wires that actually get fabricated on the die, encapsulating transistor-level design knowledge in automated design tools, and using such tools appropriately within existing ASIC design flows. One such approach is to create new design-specific cells on-the-fly at each optimization step in an ASIC flow, logical and physical including generating all views necessary for using the newly created cells within the ASIC design flow.
The benefits of proper use of transistor-level optimization within ASIC design flows range from significantly higher performance of designs and faster timing closure to improved die size, power savings, and tolerance for noise and process variation. Most importantly, these benefits can be attained at a proven and mature process node without having to incur the costs and risks of migration to the latest process node.
Debashis Bhattacharya is CTO at Zenasis Technologies, a provider of transistor-level optimization tools.