The amount of time spent on verification now exceeds the amount of time spent on design, comprising up to 70 percent of the total development effort, and the cost of failure continues to increase. The key problem: current verification methods cannot deliver the verification effectiveness and efficiencies designers need to keep pace with growing chip complexity, especially for 90 nanometer design and below.
Today's economy demands that you hit a narrow market window with the "right product that is designed right." In other words, the product has to do what the marketplace needs and wants, and it has to do it correctly. This leaves no time to respin the product if you get it wrong.
Companies need to boost verification productivity, but how? First, designers need to prevent bugs. Reuse helps tremendously in this respect, but it also introduces its own class of interface and usage bugs.
Second, designers need to find bugs with less effort while finding a wider spectrum of bugs. To achieve this, a methodology change is in order. The new verification approaches will continue to be simulation-centric because, let's face it, simulation continues to be very effective.
I believe that the key to more effective and efficient verification methodologies is the inclusion of assertions, which establish a more dynamic approach to simulation-based verification. The simulation engine must support assertion-based verification (ABV), testbench automation, and coverage-driven verification, since pure testbench driven simulation alone will not detect bugs efficiently and effectively enough to close the verification gap.
Assertions are formally captured statements about the functional intent or implementation correctness of a design. ABV complements traditional simulation by providing a number of benefits: increased design confidence, enhanced observability, and improved debug productivity. Assertions not only verify which aspects of the design have been activated, but also determine the correct operation associated with these activations.
ABV is critical because this methodology allows the designer to discover and diagnose deeply buried design flaws, which impact the ability to deliver products in competitive time-to-market windows. The use of assertions enables new verification capabilities, such as static and dynamic formal analysis, structural coverage metrics that truly identify that design functionality has been verified, and coverage-driven verification all in a single environment.
To enhance ABV methodologies, the designer needs to adopt a simulation-centric verification environment that supports standards, including SystemC, SystemVerilog, and PSL. Standards support is also critical for sustainable design reuse methodologies that allow you to protect your investments in designs, tools, and verification flows. The ideal simulation technology supports large capacity verification for system-level design and manages the complexities of integrated digital, analog-mixed signal, software, and hardware-assisted verification.
While assertion-enabled simulation surpasses current methods to narrow the verification gap, it's still insufficient; some logic is very difficult or impossible to verify using just simulation. But the addition of formal and dynamic methods truly exploits assertions by increasing observability and the speed of finding bugs.
An example of this is clock domain crossing and metastability verification. These advanced tools perform static verification, based on formal algorithms, to search for bugs exhaustively in minutes, compared to days or weeks in a simulator.
We also need to consider the interoperability of tools for increased productivity. Coverage-driven verification enables design teams to realize the value of integrated assertions, coverage, stimulus generation, and simulation—all in a single tool.
By combining the best attributes of simulation with assertion and formal techniques, your design team can construct a tool flow for block and chip level verification. The integration of these technologies maximizes coverage to find the most bugs and, when part of a standards-based environment, provides a consistent flow across multiple verification engines: simulation, formal analysis, and emulation.
I believe we are on a new path to exciting possibilities in the verification industry.
Robert Hum is vice president and general manager of the Mentor Graphics Design Verification and Test Division, which now includes the recently acquired 0-In Design Automation company. He can be reached at firstname.lastname@example.org.