SANTA CRUZ, Calif. Claiming a new capability for the EDA industry, Averant Inc. this week is introducing an automatic verification tool for timing exceptions, including false and multicycle paths. Averant's SolidTC claims to eliminate a time-consuming and error prone manual inspection.
False and multi-cycle paths are signal paths along which timing errors cannot actually occur, even though it may appear that way to a timing analysis tool. If they're not identified as timing constraints, synthesis tools will waste time trying to optimize them and static timing analyzers will report them as errors.
But until SolidTC, said Ramin Hojati, Averant CEO, there's been no good way to verify that a false path is really false. "You have to look for a set of things that you believe cannot occur," he said. "Things get really complicated. Even to experts it's not obvious that a path can't carry delay."
To use SolidTC, users simply input their RTL file and Synopsys Delay Constraints (SDC) file. Hojati said the tool has been run on multi-million gate designs, and can handle hundreds of constraints per hour. He said Averant has worked with Magma Design Automation to test the product.
SolidTC uses some of the technology in Solidify, Averant's formal property checker, and adds algorithms to generate the properties needed to verify false and multicycle paths. But it's a separate product that does not require a Solidify license.
SolidTC is available now starting at $40,000 per year.