Altera, the programmable logic company, is expected to release its first volume PLDs on 300mm wafers, using a 0.13µm all-copper process, in the second half of this year.
The company had originally planned to ship 0.18µm chips on 300mm wafers in volume late last year. But the downturn in the industry meant the firm delayed a move to 300mm, but sees it jumping two process nodes.
Paul Hollingworth, director of marketing for Altera in Europe, said: "We'd run 0.18µm at 300mm and had reasonable yields. In the second quarter TSMC [our foundry partner] realised it did not make sense to transition 0.18µm to 300mm when people were not going to be doing designs that required more volume."
He said 0.13µm chips on 200mm wafers have better yields than the 0.18µm version at its introduction.
The device is called the Apex II EP2A70. "The benefit of PLD at 0.13µm is the sheer size: we have probably the biggest 0.13µm product — it's several square cm — and the fact that it is a 2D addressable matrix means any problem can be isolated quickly."
The main problem the company is now addressing is that of current leakage.
Hollingworth said: "It's the laws of physics — every time you take away an atomic layer from a gate array you increase leakage by a factor of 10. We are now at six layers.
"The 2A70 has 20 angstroms [6 layer] gate oxide thickness. There are not many atoms you can take out before it doesn't work at all. As we go to 0.1µn we are going to see interesting issues here."
Separately, Xilinx said its foundry partner, UMC, has produced its Virtex II chips on 300mm wafers on a 0.15µm process. It now has two fabs operating 300mm wafers, and says yields are better than 200mm equivalents.
It hit back at Altera's news: "We believe the EP2A70 to be a shrink of a 0.15µm device design, with resizing of the transistors. This explains the lack of any performance increase in the device relative to the other family member.
"The current 0.15µm Xilinx Virtex-II devices actually contain 0.12µm transistor gate lengths, and 0.10µm effective channel length."
Xilinx said the Virtex-II uses a nine-layer all-aluminium process because its own assessments found only insignificant performance improvements with copper. Xilinx maintains the Virtex-II is actually 40% faster than Altera's all-copper Apex II.
Hollingworth said that the transition to 300mm means the asic industry will struggle.
"The number of different products which it makes sense to manufacture on 0.13µm and 300mm [is determined by] minimum order quantities.
"Every single wafer will create a large number of die. With boats of 24 you are getting millions. That's fine for microprocessors, microcontrollers and PLDs but not asics or ASSPs. The cost of doing these designs increases."
He cited non-recurring engineering charges — mask sets costing $750000.
"The cost of PLD versus asic is being eroded by Moore's Law. In a few years the asic industry won't be able to exist. They will be customised ASSPs. If you are Nokia with 100 million units that's fine, but how many applications out there are there?"