Actel has increased the number of gates on its flash-memory-based FPGAs to one million as the company attempts to take designs away from asic houses. For the new family, ProASIC Plus, Actel has shifted production to foundry UMC, away from the original foundry for the ProASIC, Infineon Technologies.
The ProASIC Plus family of chips covers a range of densities from 150000 gates to one million. Two of the bigger devices are sampling now with others to follow during 2002. Volume production is expected to begin in the second quarter.
The Plus family, based on a 0.22µm process, has been under development for 18 months and follow on from the original ProASIC 500k series.
Actel is looking to encourage migration from asics by offering many similar features within the Plus family. Because they use on-chip, non-volatile memory, the devices can be live at power-up and require no separate configuration memory, in contrast to SRAM-based FPGAs.
As with the original ProASIC family, the company says that existing asic design tools, from suppliers such as Cadence Design Systems and Synopsys, can be used for Plus.
The Plus family has a number of additional features beyond those in 500K. They include support for multiple phase-locked loops and up to 198kbit of dual-port embedded SRAM.
The Plus chips have two clock-conditioning blocks, each holding a PLL core, delay lines and clock multiplier and divider units.
To protect a chip design, a multi-bit key can be encoded to prevent any attempt to read or alter configuration settings and reverse engineer intellectual property within the array.
Actel plans to offer a service allowing FPGA designs to migrate to asic production for high volumes.