First it was SRAMs for communications, then DRAMs for PCs. Now fifo memories have been given the double-data rate (DDR) treatment.
IDT has developed a family of fifos that uses the DDR approach of transferring data on each clock edge to push speeds to 500Mbit/s on each pin.
The company has specified devices running at clock speeds up to 250MHz and plans to make chips with up to 5Mbit of memory in configurations with 10, 20, 30 and 40bit parallel interfaces. The extra bits will be used to mark frame or packet boundaries.
To maintain the phase relationships between clock and data traces on the PCB, IDT has opted to use a similar echo-clock scheme to that employed by the new generation of quad-data rate SRAMs being built by IDT as well as Hitachi, Samsung, NEC, Micron Technology and Cypress Semiconductor.
Instead of mandating a signalling scheme for the TeraSync memories, IDT has decided to offer 2.5V low-voltage CMOS, 1.8V HSTL or 1.5V HSTL. The devices will also support single-data rate signalling on one side and DDR on the other for rate-matching designs.