A team based at STMicroelectronics' (ST) central R&D lab in Agrate, Italy, has built a processor with a dynamically programmable instruction set. The work will be presented at the Custom Integrated Circuits Conference in Florida in mid-May.
The team has combined the Xtensa processor core, developed by US-based Tensilica, with an embedded FPGA architecture designed by M2000, a French start-up. M2000 is headed by the team that designed the emulation technology bought by Mentor Graphics in the mid-1990s and used in the SimExpress machines.
The embedded FPGA communicates with the Xtensa through the processor's instruction extension interface so that it can be used to implement custom instructions.
One problem identified by the team early on is the speed difference between hardwired logic and its FPGA equivalent.
As custom instructions in the Xtensa follow the same pipeline as the normal instructions, this could have resulted in a 10-fold slowdown in the processor's overall speed.
The ST team put together a clock control scheme where the processor runs at full speed while handling normal instructions. For custom instructions, the embedded FPGA clock is synchronised with the main processor clock if the programmable logic runs slower than the normal pipeline speed.
A type decoder works out whether the embedded FPGA clock needs to take control by looking up the processing overhead of each custom instruction in a table. The designers allowed for four different speeds.
Although the embedded FPGA core is used primarily for datapath functions in the ST design, the Flexeos core developed by M2000 uses a conventional macrocell design. It divides the array into clusters of logic cells that each implement a four-input look-up table and a register.
On a 0.18µm process using six layers of metal, the chip made by ST measures 30sq mm but is pad- limited. The actual processor core size is 20sq mm, of which 8sq mm is taken up by the embedded FPGA. About another 6sq mm is taken up by embedded memories and caches.
Running at 100MHz, the embedded FPGA core can be reconfigured in about 500µs. The team has reported speed-ups of four to eight times on face recognition algorithms using instructions implemented in the embedded FPGA.