Cadence Design Systems has picked up the exclusive rights to sell NeoLinear's analogue design tools, kicking off with a library cell-design package.
The deal comes at the same time that Cadence has inked deals with PDF Solutions and Silicon Metrics to integrate support for process simulation and library characterisation into its tools.
The deal between Cadence and NeoLinear encompasses both NeoLinear's current and future tools, which will include a circuit synthesis tool called NeoCircuit.
Tom Beckley, CEO of NeoLinear, said: "This is a real innovative business model that we have come up with. It can revolutionalise the way that analogue design is done."
Beckley said the company wants to stay independent but that management realised that NeoLinear would need more extensive sales channels if it was to stay independent. Like other cell-analysis tools, NeoLinear has tied its tools into Cadence's Virtuoso XL layout editor.
"Everyone we went to said they wanted local support and they wanted integration to Cadence," said Beckley.
NeoCell is used to generate analogue cell designs in Virtuoso format based on constraints supplied by an engineer. The tool is intended to remove a lot of the drudge work that analogue engineers typically have to perform to generate valid analogue cells.
Beckley said the constraints are designed to handle typical requirements such as symmetry and matching in analogue cell circuits.
The company is working on future offerings past the forthcoming NeoCircuit, which will encompass I/O cell and RF cell design.
"NeoCircuit will be used to size and optimise circuits. We have future work on I/O and RF but the RF tool will be some years down the road," said Beckley.
Paul McLellan, corporate vice president of solutions marketing at Cadence, said: "The revenues we make will be split between us."
He added that the deals with PDF and Silicon Metrics are not to sell tools directly but to build tighter integration with Virtuoso and other Cadence tools.
PDF's CircuitSurfer tool will be used to help yield-optimise cell and circuit designs. The tool analyses designs to gauge the effect of process variations on chip yield before the mask stage.
"The CircuitSurfer simulations are accurate to do yield predictions before tapeout. The alternative to accuracy is pessmism. Companies may invest billions in a fab but end up with no better performance because you have to guard-band so much."
Beckley added: "We want to take this knowledge and bring it up earlier in the design cycle, bring the information into NeoCell and NeoCircuit."
The deal with Silicon Metrics will see the library characterisation tools developed by Silicon Metrics integrated with Cadence's Spectre simulator.
"We have recently been investing in features for Spectre that concentrate on library design where, traditionally, we have been concentrating on circuit simulation," said McClellan.
"We are developing software to peform things such as setup and hold checks in Spectre directly [to make characterisation more efficient]. There will be a version of SiliconSmart that runs with Spectre."