Esterel Studio, a system-level EDA tool that its developer claims is being used by Texas Instruments to help design digital signal processors for mobile phones, is being unveiled to the broader public at DATE this week. Esterel Studio is the first commercial EDA tool to use Esterel, a research language that can be used before hardware/software partitioning to describe the control portion of embedded systems.
Esterel supports the formal description and proof of behaviour of embedded systems, its proponents claim. "Esterel is a synchronous reactive language with very clean FSM [finite state machine]-like semantics and hence is ideal to express implementation-independent control-dominated systems," said Alberto Sangiovanni-Vincentelli, professor of electrical engineering and computer science at the University of California at Berkeley.
Research work on the language conducted largely in France and estimated at 120-man-years' effort prompted the formation of Esterel Technologies SA, the developer of Esterel Studio, in Guyancourt, France, in April 2000. The bulk of the research work on Esterel was conducted at the Ecoles des Mines de Paris, at two other French research institutes (CNRS and INRIA) and at Cadence Labs.
"We used Esterel as an input language for Polis, the Berkeley hardware/software co-design system," said Sangiovanni-Vincentelli, a Cadence cofounder and board member who helps direct the work of Cadence Berkeley Laboratories. "We liked Esterel for its rigorous approach, which allows [you] to run formal verification on the description of the system, and for its expressiveness. The clean semantics allow [you] also to synthesize efficient C code from Esterel.
"The drawback of Esterel, as with any FSM-like language, is the state-explosion problem when the communicating FSMs are merged together for either formal verification or synthesis," he said. "The essential novelty for Esterel Technologies is providing a graphical-entry language that offers designers a simpler mechanism to describe their design over classical Esterel."
Esterel Studio's graphical user interface helps engineers capture system specifications. The tool can then be used to formally prove system properties before automatically creating C-language application code or VHDL to describe systems.
"You can show whether the system can go to any nondesirable state or through any nondesirable transition," said Hassan Laasri, vice president of marketing and business development at Esterel Technologies. "Behind the graphics, we have algorithms that capture the essence of the system, so people do not have to write their own modules in Esterel."
Esterel Studio is also expected to be used as an optional point of entry to the VCC system codesign tool from Cadence Design Systems. Cadence has no plans to include native Esterel support within VCC but is working to interface VCC to Esterel Studio in response to customer requests, according to Frank Schirrmeister, director of product management for co-design technology at that company.
"VCC is able to deal with a number of different input languages. Esterel Studio is an entry technology we are looking at for control code," Schirrmeister said. "It's elegant. You have the ability to apply formal methods that are independent of implementation."
"Cadence VCC is an integration tool and today is based on a CFSM [communicating finite state machine] semantic model that's being extended to cover data-flow like designs," noted Sangiovanni-Vincentelli. "As such, Esterel Technologies tools can be fairly easily linked into VCC."
"In this case Esterel Studio will be an intellectual-property-authoring mechanism for control-dominated systems. The IP entered, verified and even synthesized with Esterel Studio can be integrated in the VCC environment."
The tool comprises a graphical editor, a graphical simulator, formal verification tools (FVTs) and Esterel code generators. According to information at the Esterel Technologies Web site, the output from Esterel Studio can be C or Java, for software, or VHDL, if the system is intended to be a purely hardware implementation.
"Java and VHDL output are possible, but they are really engineering capabilities right now," said Laasri. "They are not yet supported in the product, but [such support] is planned."
Laasri said the company had kept a low profile over the past 12 months while it worked with lead customers. He said Esterel Technologies now has 33 licenses with Dassault Aviation, where Esterel Studio is being used to develop embedded software for the Rafale and Mirage 2000 military aircraft; 15 seats with Thales, for the development of electronic commerce protocols; and three seats with TI, for the specification, verification and testing of DSPs for mobile phones.
Intel is another licensee, as is PSA Peugeot Citroën, a French automobile maker using Esterel for the design of smart dashboard systems and engine microcontrollers, Laasri said. References include Motorola, Philips Semiconductors and STMicroelectronics, he said.
He said Esterel Studio represents the control part of DSPs, microcontrollers and embedded computers, adding that the language really operates on finite state machines (FSMs).
Part of the DATE launch for the Esterel Studio tool is a move to version 3.0, which Laasri said supports links to C modeling of hardware.
"Today we can't contribute to [the definition of] the datapath, but in 2001 there will be a new release of Esterel Studio that will handle that," Laasri said. Version 3.1 of Esterel Studio will support the Unified Modeling Language, he added.
The Esterel compilers and analysis tools represent Esterel programs in an internal circuit form. Speed optimisation is obtained by minimizing the critical path of the circuit.
Meanwhile, a team comprising Esterel Technologies, Cadence Design Systems, Ecoles des Mines de Paris, INRIA and Thales has been selected by the French Network of Research in Telecommunication to further develop Esterel and Esterel Studio under a project called Syntel.
Syntel's objective is the creation of a hardware/software co-design platform for developing wireless protocols. Under the project, the team will integrate the Esterel C Language, developed at Cadence Berkeley Laboratories, into Esterel Studio.