Ikos has developed an in-circuit logic emulator that can hold 15 million gates of logic and provide information about each internal node without recompiling the design.
Linda Prowse Fosler, vice president of marketing for Ikos, said: "All nodes are visible by default. There is no impact on performance."
The VStation-15M is the result of the company moving to Xilinx' Virtex series of FPGAs. Although the FPGA company is now moving to Virtex-II, Ikos tends to move to a new FPGA architecture once the family has been shipping in volume for some time.
"We like to follow one generation behind the state of the art," said Fosler.
To make all of the logic nodes visible, the company has decided to distribute the logic analyser functions throughout the box. On previous generations, the logic analyser was held on a dedicated card. Now, there is a set of logic analyser circuits sitting on each of the logic-array cards.
With the change to new FPGAs, the company is claiming compile rates of 5 million gates per hour.
"The Xilinx software that we rely on is very much improved for Virtex. We were getting 2 million to 2.5 million gates per hour," said Fosler.
For very large designs, Ikos supports multi-module compiles in which the design is automatically partitioned across a number of the company's emulators.
"Logically, it is seen as one box. The design is arbitrarily partitioned across them," said Fosler.
In moving from the previous 5 million gate generation, the company has increased the number of independent clock domains that the emulator will support. The number has gone up to 30 from 15, with the ability to generate an unlimited number of sub-clocks from each of them.
Ikos is now working on a direct memory interface between workstations that run simulations and the emulators themselves. The company already uses an interface scheme that it reckons is much faster than the Verilog programming language interface (PLI), because it relies on passing information in the form of complete transactions rather than synchronising the two environments at each discrete event in the way that PLI does.
The new scheme will put shared memory between the workstation and the emulator so that each can access data directly.
"Shared memory is an enhancement which is on its way. It will reside on the interface between the hardware and the software environment," said Fosler.
The company is undecided as to whether a shared-memory interface specification will be put forward to the recently formed SCE-API consortium that is working on co-modelling interfaces for emulators. If it is included, it will be in the phase-two spec.
"Eight months from now, we hope to release phase two," said Fosler, adding that some work is being performed in the group to help independent vendors come up with designs that conform readily to the SCE-API.
"The standard stops short of the hardware implementation details. But from the software side it will be as common as we can make it.
"The consortium has put together plans to fund a full reference implementation. We will fund a third-party to do it," said Fosler.