Cadence Design Systems and Agere Systems (formerly Lucent Technologies' microelectronics company) will announce a partnership at this week's DATE conference to develop tools for chip I/O-planning. Such a tool will allow the design of ICs and chip packages together, functions that are largely separate today.
The partnership is expected to result in a new tool available in the fourth quarter of 2001. Part of Cadence's SuperChip initiative, the chip I/O-planning tool will be used to develop chip packaging that considers mechanical feasibility, electrical concerns, and routability.
Right now, said Joel McGrath, marketing manager for Cadence's IC packaging products, there's a "discontinuity" between IC design and packaging. "Chip design takes place without consideration of the package," he said. "This alliance will develop methodologies and tools that address that gap."
Many chip design firms, said McGrath, are "working in the dark" when it comes to IC packaging.
Agere reckons it is doing a little better. The company has internal tools that make it possible to run some feasibility studies of packaging alternatives, and to drive IC placement and routing with packaging constraints.
"Our tools take us part of the way to a complete solution, and we're looking to Cadence to add more features," said Donald Hawk, consulting member of Agere's technical staff. Specifically, Hawk said, Agere wants to bring electrical constraints and routability into its packaging solutions.
Cadence already offers both IC design tools and packaging tools, but not the chip I/O planning that the Agere partnership addresses. "Chip tools typically end the design process at the I/O buffers," McGrath noted. "With chip I/O planning, you bring the package and the silicon together in the same environment."
Chip I/O planning will allow designers to consider packaging tradeoffs. One desired capability of a chip I/O planning tool is the extraction of interconnect from the I/O buffers out to the package pins. Another is power distribution analysis. Designers may also be able to identify differential pair opportunities.
"The packaging tools we're aware of really take the die as a finished product," said Hawk. "We're dealing with a chicken-and-egg scenario — the IC designer is asking what the package looks like, and the packaging designer is asking what the chip looks like."
Hawk noted that chip designers need to know where pads are located on a chip, so they can start planning from a system-level perspective. Cadence will help, Hawk said, by bringing routing into the picture and showing how signals map to the package.
The partnership agreement includes a commitment by Agere to provide Cadence with internal software and engineering support for a two-year period. Agere will have first access to new software developed by a joint Cadence-Agere team. Then, the functionality will become available on a commercial basis. The new product that results from the partnership will be marketed by Cadence's PCB Systems Division.
"We get more capability and a commercial product we can share with customers, so we can look at complete system level designs," said Hawk.
Richard Goering is managing editor, design automation for US sister newspaper EETimes.