Californian startup Adaptive Silicon has publicly unveiled the design that the company will use to bring its own form of programmable logic to ASICs.
In a break from traditional programmable-logic arrays, Adaptive has used an approach that borrows from the bit-slice logic used in the 1970s to construct computer designs from medium-scale integration devices.
As reported in Electronics Times (Print: 9 August 1999), the company has used an architecture based on arithmetic logic units (ALUs), in contrast to the lookup tables used by most SRAM-based FPGAs.
The basic FPGA cell is based around a 4bit ALU in an architecture reminiscent of the early TTL chip, the 74S181. In the Adaptive array, SRAM cells control the logic cells that drive the ALU functions.
The company has extended the operations that the ALU can support to make it more amenable to random logic functions. Although the founders of Adaptive have a background in reconfigurable logic, vice president of marketing Ralph Zak said the company wanted to avoid its array being regarded as a purely datapath-oriented architecture.
"A 4bit ALU is very efficient for arithmetic work but it can also act as a three-input, one-output lookup table," said Zak.
"In an FPGA, about 60 to 70% of the area is consumed by routing resource with only 10 to 15% used for the programmable elements. That means the overhead for the ALU controller is miniscule, so we have extended it to handle control as well as arithmetic functions."
"We put in sufficient routing to handle random logic. We could have got away with 30 to 40% less routing resource of we wanted to but it would have pigeonholed the array into something more datapath-oriented.
"Of the customers we spoke to, many people felt much of the risk in their designs was down to control logic."
For control functions, each logic cell contains multiplexers so that the 4bit ALU can act as a wide-input logic functions such as a 12-input OR or AND gate.
The need to support control logic has not stopped the company from adding arithmetic support. As with many SRAM-based FPGAs, the company has built in a carry-chain structure.
"Most FPGAs use a ripple carry. We use a full carry lookahead structure for very fast counters," said Zak.
The company is working on a synthesis back-end for its architecture and has cut a deal, to be announced next week, with a specialist in FPGA synthesis.
Initial software support will come in the form of DesignWare-compatible logic elements for users of Synopsys' Design Compiler.
"We have built a library that corresponds to the DesignWare elements. We substitute them with our macros in the mapping phase," said Zak.