Belgium-based Frontier Design has developed a new version of its C-based hardware design tool to deal with programmable logic as a target and which adds SystemC as an input language.
The move is set to bring ART Designer into competition with the DK1 design environment for the Handel-C language, recently introduced by Abingdon-based Celoxica.
Up to now, the ART technology has largely been pitched at ASIC designers, particularly those needing to explore candidate architectures for low-power systems, so Frontier has added optimisations specifically for FPGAs in the new version.
Frontier CEO Herman Beke said: "FPGAs have very special characteristics that have never been adequately addressed by system-level design tools. This is the space we are addressing with ART Designer 2.3."
The FPGA changes include the ability to put registers into look-up table memory, "single-cycle resource creation" and microcode compaction techniques.
The single-cycle resource creation allows a designer to create a special super-instruction, say two multiplies and an add, and maintain it as a resource during the design exploration phase. The tool searches the C code for any instance of the relevant combination of basic instructions and insist they are implemented as single-cycle features within the FPGA.
This increases the parallelism of the design and plays to one of the strengths of the FPGA architecture - greater parallelism at slower clock frequencies.
The microcode compaction feature is, in effect, the ability to create a ARM Thumb-style program code compaction system for a custom hardware architecture.
A|RT Designer minimises the amount of memory required for microcode storage by using FPGA look-up tables as decoders. The technique makes use of the fact that instructions needed to control a datapath can be identified using significantly fewer bits. Similar techniques have been used on configurable DSPs such as the Infineon Technologies Carmel to reduce the impact of using very long instruction words to control a parallelised DSP architecture.
The tool analyses the source DSP code and reduces it to the smallest possible word width, and then creates the appropriate number of decoders. Memory space savings of up to 70% are possible, the company claims.
"ART Designer is the first EDA tool that automates the optimisation of FPGA memory and logic to achieve the highest throughput solution in the smallest amount of silicon," said Beke.
Peter Clarke is European correspondent of US sister newspaper EETimes.