Integrated Device Technology (IDT) has put together a commns controller for home DSL gateways that combines its MIPS-based RC32300 core with Ethernet, USB, telephony and ATM interfaces.
The company decided to put most of the necessary interfaces for a gateway on-chip, although the designers chose not to handle compression for voice over Internet Protocol calls using the MIPS processor.
Instead, the company used the 150MHz processor core to handle firewall and other protection code because of the extra vulnerability of 'always on' DSL connections.
For voice compression support, IDT recommends an external DSP. To handle non-compressed and compressed speech, the designers put a time-domain multiplexed (TDM) bus that conforms to the various de facto standards for voice buses onto the RC32355, such as CHI and GCI.
Arne Orhaug, European applications manager for IDT, says a number of companies have implemented Internet access devices without voice compression because of the extra cost and delay incurred by the VoIP compression routines but employ off-the-shelf subscriber-line interface that have a TDM port as standard.
If a DSP is used, "the output from the DSP could still use TDM," said Orhaug. He adds that to put compression on-chip would take up a lot of die space but "the long-term intention of any vendor is to put the compression on-chip".
To offload the processor from dealing with straight transfers between the various communications interfaces, IDT has implemented a 16-channel direct memory access (DMA) controller.
"The [processor] core is intended for statistics and quality of service functions. We don't burden it with moving data," said Orhaug.
The DMA controller can receive network packets without involving the processor through a mechanism that the company calls virtual caching.
An eight-entry content addressable memory in the controller watches for ATM virtual channels on the DSL connection that the gateway is using. Cells with addresses stored in the cache are stored in the gateway's memory automatically by the DMA engine.
The DMA controller handles scatter-gather transfers, managed through linked list structures by the processor, and accesses that are not aligned to 32bit boundaries.
The ATM interface used for the DSL connection has some hardware support for adaptation layers with the rest performed in software. The data-oriented adaptation layers perform cell assembly and disassembly without intervention but the voice-oriented AAL2 has to be done in software.
"The standard for this [AAL2] was set quite recently so it was not possible to implement it in hardware. It's very different from other AALs and can support several calls per cell," said Orhaug. "There is also the question of how popular voice over ATM will be."
The Ethernet interface supports a standard media-independent interface for connections to regular physical interfaces or the HomePNA devices for phoneline networking. But Orhaug says interest in HomePNA seems to be waning "mainly due to the reliability problems that have been seen".
The company is building the RC32355 on a 0.18µm process at its fab in Oregon. To save power, the chip will run from two supply voltages, with the core running at 2.5V and the I/O at 3.3V.