Altera is challenging the Virtex-II family from Xilinx with FPGAs boasting up to 400Gbit/s bandwidth.
The Apex II family doubles the amount of memory — but the in-crease does not go as far as that on Virtex-II — and increases density to 90000 logic elements, equivalent to seven million system gates, says Paul Hollingworth, dir-ector of marketing for Altera Europe.
But the main upgrades are in interfaces for telecoms, which makes up 75% of Altera's European sales.
Hollingworth says it is not time for larger amounts of memory: "We think, at the moment, there is a period of a couple of years during which people will be happy with double the memory.
"The next family will go much higher when designers start using a lot more memory because of embedded processing. It's like the asic business. That went from 20% memory and 80% logic to 80% memory and 20% logic over three years because of the embedding of processors."
Altera has picked a new metric to measure the capacity of FPGAs, attacking the use of 'system gates' by arch rival Xilinx.
Altera wants to use registers as the main metric for measuring density. This is what leads to its latest Apex II family starting with the EP2A15, with just over 15000 logic elements and so 15000 registers. This is the equivalent to 1.9m system gates, or 600000 usable gates, says Altera. The family will run up to the EP2A90, with just under 90000 registers and the equivalent of 7 million system gates or 4 million usable gates, due at the very end of this year.
Altera has not made clear whether registers in the I/O cells are included in the total register count. The Apex II family has six registers in each I/O cell that are needed to maintain high speeds. The high-speed I/O adds around 10% to the die area of the devices.
Those I/O cells handle low-voltage differential swing (LVDS) protocols such as Rapid IO, Utopia and POS-PHY. The chip supports 36 input pins and 36 output pins of 'true' LVDS at 1Gbit/s each backed by dedicated 8bit wide serialiser and deserialiser (SERDES) logic. A 100MHz clock is fed to 10x PLLs to get the 1GHz clock.
There are another 56 input and 56 output channels of 'flexible' LVDS at 624Mbit/s on the smaller devices. They require more registers to be used from core resources to build the SERDES logic. On the larger parts this will be increased to 88 pins of each.
The cells also handle differential protocols such as low voltage PECL, PCML and AMD's HyperTransport, as well as single ended protocols such as HSTL, SSTL and PCI-X.
Clocks and memory buffers are just as vital to increasing the throughput, so Altera has included the clock data synchronisation technology that was introduced with the Mercury family that allows a master system clock to control all the devices on the board and 12 clock domains within the chip.
The company has also added 'true' dual-port memories that can read and write simultaneously. The I/O blocks also support all the memory interfaces -- zero bus turn around (ZBT), double data rate (DDR) and quad data rate (QDR) SRAM as well as standard SDR and DDR SDRAM.