Agere Systems has put together a single-chip comms engine for add-drop multiplexers that pulls together eight million gates. But while designing the chip, the company found that the verification tools needed to check its work almost ran out of steam.
Agere's Ultra Mapper is the follow-on to the Super Mapper device launched in 1999, and is able to combine traffic from 84 T1 or 63 E1 channels on to a 155Mbit/s OC-3 link. Four used together will handle a 768Mbit/s OC-12 connection as each of them can terminate the higher speed interface.
The eight million gates on the Ultra Mapper come from a variety of existing, redesigned and new intellectual property (IP) cores that Agere has built up. Part of the design involved porting the VHDL blocks from the older COM1 pro-cess to the company's current 0.16µm COM2 process.
The IP reuse approach helped cut design time by half, says Glen Miller, technical manager of the design team. "But the verification process took one-and-a-quarter times longer than for the engine's predecessor," he added.
To check the design, Agere used a combination of verification techniques, including random and directed tests built using Verisity's Specman environment. It made extensive use of hardware acceleration but had to split such a large design across machines.
"We are using the largest machines that Ikos has available but we had to split the design, even with the largest box," said Miller. "Access to a larger emulator would have helped."
Agere also found that the size of the design meant engineers had to avoid using some older workstations at the group's disposal.
The team used 64bit environments extensively to fit the design into memory during verification. The design was split into modules during much of the early verification phase to speed up simulation.
Harry Kalvonjian, design director, said: "Simulation speed is limiting us, so we are looking at new languages, such as SystemC."