Researchers at Stanford University have developed a way of speeding up the display of chip layouts by borrowing techniques from the world of 3D animation.
Jeff Solomon and Mark Horowitz used mip-mapping, a technique employed in 3D graphics to store textures that need to be mapped on to a surface. These display the interconnect for large chip designs in place of vector graphics.
With vector graphics, unless the layout is viewed at high detail, displaying a large number of wires or transistors each one pixel wide on a screen results in a block of solid colour with no apparent detail.
Solomon and Horowitz used a variant of mip-mapping — a technique used to cache textures at various resolutions — to hold the image information for a chip. The program can zoom in and out by loading different mip-maps and scaling them.
To cut down the amount of memory and compute power to build the mip-maps, the Stanford researchers used a tiling scheme coupled with multi-threading techniques for offline processing.