Toshiba is building a RISC processor using a novel approach to routing that could reduce die size and boost performance without any change in process technology.
The processor is based on work by design automation company Simplex Solutions. It has applied a technique that has been available to designers for a number of years but has rarely been employed: the use of 45deg routing as an extra degree of flexibility beyond the right-angled Manhattan routing used in practically all chip designs today.
In principle, this delivers an extra freedom in routing that could shorten average interconnect distances and reduce the number of vias needed to complete the connection between two transistors. This in turn would give size and speed improvements.
Jan Willis, vice president of business development for Simplex, said: "We have seen plenty of advances in manufacturing. It's about time there was a breakthrough on the design side."
Simplex reckons that it can reduce the overall amount of interconnect by 20% using the technique.
Toshiba has helped fund the Simplex project, which started three years ago, and will pay royalties to Simplex on the technology if the designs it takes to fab do prove smaller and faster.
Toshiba has yet to say when it will tape out the diagonally routed processor but Willis said the design is 100% auto-routed and that the Japanese company "will be the first to get working silicon."
However, companies already in the place-and-route market argue that the extra complexity 45deg routing brings may not outweigh the vaunted benefits.
Graham Curren, head of marketing for Avant in Europe, said: "Today's users are looking to improve productivity and time-to-market for designs at more than 50 million gates. Forty-five degree routing works against this desire, by needlessly complicating the design process, without adding any apparent benefits."
Paul McLellan, corporate vice president of marketing for Cadence Design Systems, said: "It is interesting technology but it is far from revolutionary. Forty-five degree routing has been around for years. We have history in 45deg routing but there was very little interest from the customer base.
"Many semiconductor companies are run by the fab people and they have design rules that the designers have to use."
He added that those design rules almost always assume right-angled routing.
"But if it turns out that people want [45deg routing] we will do it," McLellan added.
Cadence bought Cooper & Chyan Technology in 1996 to get its PCB routing technology and use it in both chip- and board-level design systems.
"For anyone who has a PCB router, the basic technology is all there," said McLellan.
Avant's Curren said that, although 45deg routing is used in PCB design, the greater density of interconnect in IC design causes problems: "Even more complex all-angle routing is used in our Encore packaging tool and it is great for that purpose, but it does not scale to full IC layout."
He added that the use of 45deg routing will complicate the design of verification tools needed downstream from routing.
A major concern is how the use of 45deg traces will affect mask making. To deal with the problems of making and checking masks, as well as other yield-related issues, Simplex has formed the X Initiative consortium.
"The heart of silicon manufacture is in mask production. OPC [optical proximity correction] exploded the data they had to deal with and they felt they were not part of the solution," said Willis.
"Much of the technology exists in the supply chain today and we wanted to ensure that the suppliers were involved."
Consortium members in the mask industry include Etec-Applied Materials, Toshiba Machine, Dai Nippon Printing, DuPont Photomasks and KLA-Tencor. Numerical Technologies and PDF Solutions have signed up as design-analysis companies.
Etec and Toshiba have claimed to be able to work with diagonal paths with their respective raster-scan and vector-based mask-pattern generation techniques.
In the initial phases of the project, Simplex will restrict the number of layers that use diagonal routing. The others will use conventional Manhattan routing, although it is possible to use diagonal "jogs" on some.
"We are preserving layers one, two and three. By having layers four and five rotated by 45deg and then by 90, you get almost all of the possible gain," said Willis.
Although Numerical is an early member of the X Initiative consortium, Willis said that the first masks to use the diagonals are unlikely to make much use of optical correction techniques because layers four and five typically use more relaxed geometries than the base transistor and low-level routing layers.
"Phase shift masking will not be needed on layers four and five until 0.1 microns," she said.
However, through its early 2000 acquisition of Transcription Enterprises, Numerical has important technology for transferring mask data.
"We are working with Numerical to keep the data size down," said Willis.
Willis said the 20% reduction in interconnect comes from two factors. Close to three-quarters is from routing savings from being able to use diagonals. The remainder is from placement optimisations allowed by more efficient routing.
The company is preparing both a router and a placement engine. The router uses what the company calls "liquid routing". Almost all routers dedicate each layer of metal to one direction: horizontal or vertical. On layers four and five, the Simplex router will be able to choose other directions than the predominant north-east and north-west directions. As a result, the router should use fewer vias.
Cadence's McLellan said that routers tend to keep to one main direction on any layer to reduce the probability of having paths blocked unnecessarily.
"There is a predominant direction is PCB routing today. Broadly speaking, you are not going to move away from that," said McLellan.
The placement engine is not designed to replace those from existing place-and-route tools. Instead, it will take the placement generated by tools such as Synopsys' PhysOpt and Cadence's Silicon Ensemble and optimise them for the liquid router. The flow developed for Toshiba is based on Synopsys and Cadence tools acting as the front-end for the Simplex software.