The array technology behind the reconfigurable DSP launched last week by Bristol-based Elixent is designed to allow systems to be partially or wholly reconfigured on-the-fly. The target application is digital cameras, but the technology is also being looked at for digital camcorders and next-generation mobile phones.
The array of 4bit arithmetic units is designed to replace hardwired datapath logic with a programmable equivalent. With between 400 and 1000 units, each with its own set of 16 instructions, the array can be tuned to the requirements of a particular algorithm or built with spare capacity to handle future algorithms.
Alan Marshall, chief technology officer, says that to compress a megapixel image using the JPEG algorithm would take "significantly fewer than 1000 ALUs" operating at 100MHz. With 100 ALUs occupying 1mm2, an array of 1000 will occupy a square hardware bus with sides just over 3mm. Kenn Lamb, chief executive, says that, while this is around four times less dense than an asic standard cell, it is also about four times smaller than the same functions in an FPGA.
The 4bit granularity means that different parts of the algorithm can be handled with the appropriate bit width to the task, and that bit width can be increased if more performance is needed, even in realtime, while the algorithm is running.
Elixent has worked on the interconnect between the ALUs. Each ALU can link directly to any other ALU via an uncontested 4bit-wide interconnect made up of short, medium and long lines.
A key point for reconfiguring any device in realtime is the size of the configuration file and the bandwidth for getting that data to the re-programmable elements, and Elixent has focused on this. Each element requires less than 100bit to be configured, giving a configuration time of "tens of microseconds", says Marshall.
The technology will slot into existing asic design flows but requires a dedicated I/O block to take data from the on-chip bus and feed it into the array, and to get the end data back to the bus. Elixent says it is looking at providing standard blocks for this based around common bus protocols such as ARM's Amba hardware bus.