Altera is trying to create a common on-chip channel for communications functions using an approach that has made ARM's Amba hardware bus the most commonly used peripheral bus in system-on-chip designs.
Altera has made the specification for its Atlantic channel available on the web and has, so far, signed up two intellectual property (IP) core developers, to build functions that are compatible with it.
Pat Mead, technical marketing manager for Altera, said the move is designed to "mediate the I/O standards war".
"There is something of a problem going on in the industry. Several standards bodies have created different interfaces to glue communications chips together. People have had to design their own interfaces to ASSPs," said Mead.
He said Altera developed its own bus instead of picking an interface such as CSIX to reduce the implementation overhead.
Pat Mead, technical marketing manager for Altera, said: "AMCC or Vitesse won't put Atlantic onto a standard product. We are able to link them by bridging to a common interface. People don't want to choose the products from one manufacturer. They want to mix and match."
Altera originally developed the Atlantic interface to connect its own communications IP cores together. For example, a packet processor would communicate through a FIFO with a Pos-Phy interface core using Atlantic so that the FPGA could relay data to a dedicated SONET or SDH device. Because a growing number of networking designs are mixing packet-based traffic with constant-bitrate systems, they may be packet-voice systems that then relay data using SONET or SDH frames.
As a result, the Atlantic designers opted to give the interface to handle both packet- and cell-based data. The interface uses one-way, point-to-point data links with a set of control signals to let it handle variable-length packets as well as fixed-length cells.
The company has designed a bridge compiler, for Pos-Phy interfaces initially, to deal with point-to-multipoint connections. It lets developers add address bits to the input port of the bridge so that the master can determine which output port from the bridge carries the data.
The Atlantic interface has been designed so that it can vary in terms of bus width and clock speed. It is a fully synchronous bus and will scale from an 8bit-wide version to more than 64bit.
As well as standard start-of-packet and end-of-packet signal lines, the interface can carry a parity signal, an error line and a set of data-empty signals.
The error line lets the sending unit tell the receiver that the packet in progress needs to be aborted, preventing it from passing the data further downstream. The empty lines are for wide buses and are used to show which bytes do not contain valid data at the end of a packet. For example, a 53byte ATM cell going over a 64bit bus will need to show that five out of the eight possible bytes contain invalid data on the last transfer.
Typically, Atlantic is unidirectional. But the bus supports an extra data-valid control line to handle the situation where a slave provides data to a master under the master's control.
So far, two suppliers — Innocor and Modelware — have agreed to develop IP cores with Atlantic interfaces.