The international committee working on the roadmap for the semiconductor industry for the next 15 years has decided to look at alternatives to conventional CMOS transistors as the brick wall that threatens the current approach to scaling looms closer.
The committee defined the brick wall in the 1999 International Technology Roadmap for Semiconductors (ITRS) as being the point at which there were more unanswered questions over how smaller feature sizes would be achieved than potential answers. In the 1999 roadmap, the brick wall loomed at 2008. In the 2001 roadmap, because some of the expected timings for process introductions have changed, it has moved forward a year.
Bob Doering, vice-chairman of the ITRS US region and a Texas Instruments senior fellow, said: "The red brick is essentially in the same place [as in 1999]. We have moved closer to the red-brick wall. But there is some porosity in the wall: things have moved in both directions."
The porosity means that gate shrinks are expected to happen faster than predicted by the 1999 roadmap. Such shrinks have been helped by image-enhancement techniques such as phase shifting.
Dr Chenming Hu, chief technology officer of TSMC, said: "Gate length reduction is accelerating faster than device pitch. Junction, metal cladding and low-k dielectric changes have been decelerated."
The ultralow-k dielectrics, needed to cut crosstalk between metal lines, have moved further out because of issues over the ability of the materials to withstand the harsh conditions of chipmaking.
Because some issues may not be resolved even by the middle of the decade, the committee has decided to look at new device structures, such as the ultrathin body silicon-on-insulator (SOI) transistor that Intel said it would start to adopt from 2005.
"We believe that, by 2010, new device structures will be required. They may be used as early as 2007," said Hu.
As well as SOI, the ITRS committee has put double-gate transistors and band-engineered transistors, based on the strained-silicon ideas promoted by Amberwave, Hitachi and IBM, on the roadmap.
"Band-engineered transistors support faster electrons and they can be used for speed improvement requirements," said Hu. He added that the double-gate category includes three main types of transistor:
the vertical transistor
the conventional double-gate structure.
Although design automation tools are expected to form a part of the roadmap, the committee has downplayed the significance of the design gap that emerged in the late 1990s.
Paolo Gargini, chairman of the ITRS committee and an Intel fellow, said: "One item discussed this morning [ahead of the roadmap announcement] is the need to synchronise hardware and software. The need to use commercial tools has also increased. But we think the design gap has decreased."
Hu added: "It has become quite obvious that some of the difficulties of using EDA to design multibillion transistor ICs have been relieved by the use of large intellectual property blocks.
"The emphasis [in the EDA roadmap] will be on place-and-route and verification."