A set of tools for asic design that dispenses with standard cell libraries almost completely is being written by a research team from Infineon Technologies' research centre in Sophia-Antipolis and the University of Montpelier.
Taking its lead from work into 'liquid libraries' by Prolific and Numerical Technologies subsidiary Cadabra Design Automation, the team is writing a set of placement and transistor-sizing engines and timing calculators as C++ plug-ins that can act as the back-end for a synthesis-driven flow.
Alexis Landrault, a member of the research team, said: "The flow is built around a common data structure and introduces a new concept: the virtual library."
Instead of developing a set of standard cells up front, the team defined a generic combinatorial logic of four nMOS and four pMOS transistors. By making or cutting connections, the one cell can yield about 3000 possible logic cells. Using a single cell structure means that the height of the placed cells stays constant and the tools are left free to size individual transistors to optimise their drive strengths.
"We can perform transistor resizing and wide-width resizing continuously," said Landrault. And sequential cells such as flipflops are made from the basic combinatorial cells as 'macroblocks'.
The synthesis tool is still provided with a cell library view, but the actual logic and placement is not generated until close to the end of the process. Delay power modelling provides information on how big each transistor needs to be.
Within a row, once placed, virtual cells can be flipped to let transistors share diffusion wells and help reduce the size of the design.
"The transistor density is close to that of standard cells," he said.
The team is continuing to work on the toolset and a timing engine that will feed back into simulation.