French design automation company TNI-Valiosys has licensed Verisity's e verification language as part of a project to link formal verification techniques with traditional simulation-oriented design checks.
The licensing deal is part of a move by suppliers of formal verification tools to get their techniques adopted in mainstream chip design flows. Conventional tools need to have the design checks written in specialised languages. However, languages for simulation-based verification such as e and OpenVera have gained wider audiences.
Jean-Luc Lambert, TNI-Valiosys's chief scientist, said: "Interfacing with e is important for us, since it helps customers who are already using e improve design quality by reusing it to formally validate their RTL models."