Sequence Design is working with library suppliers to build asic design tools that run at multiple voltages.
Vic Kulkarni, chief operating officer of Sequence, said: "Asic designs are already at 1.1 to 1.2V and we will hit the 1V barrier with 100nm processes. Multi-threshold devices are becoming more of a reality as leakage power begins to approach dynamic switching power consumption."
The company expects to demonstrate tools in what it calls the NanoCool flow at the Design, Automation and Test in Europe conference next spring.
Kulkarni said: "With the Nano-Cool flow, we will allow design exploration and partition a chip into voltage domains. We will be able to partition at the RTL level. We are looking at multi-threshold cell libraries with Artisan and Virtual Silicon. Power gating will be in the following release."
Designers are looking at power gating because of the rise in leakage currents. The technique uses transistors in the power network to put gates completely to sleep by cutting off supply current.
Clock gating just disconnects the clock from unused logic, but by cutting off the supply, leakage current can be kept to a minimum.
Multi-threshold logic libraries will let tools trade off critical path delay against threshold voltage.